Patents by Inventor Pat Allen Buckland
Pat Allen Buckland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6865615Abstract: A method and an apparatus is presented for configuring a system bus topology dynamically. In a preferred embodiment, the system bus is a Small Computer System Interface (SCSI) bus that connects a “daisy” chain of disk drives. Two types of disk drives are used: single ended (SE) “Ultra” drives capable of 20 MHz operation and LVD (low voltage differential) “Ultra Plus” drives capable of 40 MHz operation. LVD disk drives can also function in the slower SE mode. The first drive in the chain of drives may need to be connected by a cable over three feet long. This introduces signal degradation that is often overcome by introducing redrive circuitry to boost signal quality. This is an expensive solution and a much easier solution is presented: install a jumper between the last drive in the chain and the first drive. However, if LVD bus mode is used, then this jumper solution does not work and the jumper must be removed.Type: GrantFiled: July 20, 2000Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Scott Leonard Daniels, Thomas R. Forrer, Jr., Daniel Eugene Pridgeon
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Patent number: 6785783Abstract: A method and system for managing data in a data processing system are disclosed. Initially, data is stored in a first portion of the main memory of the system. Responsive to storing the data in the first portion of main memory, information is then stored in a second portion of the main memory. The information stored in the second portion of main memory is indicative of the data stored in the first portion. In an embodiment in which the data processing system is implemented as a multi-node system such as a NUMA system, the first portion of the main memory is in the main memory of a first node of system and the second portion of the main memory is in the main memory of a second node of the system. In one embodiment, storing information in the second portion of the main memory is achieved by storing a copy of the data in the second portion. If a fault in the first portion of the main memory is detected, the information in the second main memory portion is retrieved and stored to a persistent storage device.Type: GrantFiled: November 30, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventor: Pat Allen Buckland
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Patent number: 6715011Abstract: A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus.Type: GrantFiled: May 31, 2000Date of Patent: March 30, 2004Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Daniel Marvin Neal, Steven Mark Thurber
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Patent number: 6665753Abstract: A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.Type: GrantFiled: August 10, 2000Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Michael Anthony Perez, Kiet Anh Tran, Adalberto Guillermo Yanes
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Patent number: 6581129Abstract: A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.Type: GrantFiled: October 7, 1999Date of Patent: June 17, 2003Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Daniel Frank Moertl, Danny Marvin Neal, Steven Mark Thurber, Scott Michael Willenborg, Curtis Carl Wollbrink, Adalberto Guillermo Yanes
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Patent number: 6467022Abstract: A Solid State Disk (“SSD”) and accompanying logic to extend the local memory of an adapter for RAID storage devices. Use of virtual memory, representing the SSD range of addresses in the adapter address memory, allows the adapter to incorporate the total memory into the adapter memory structure. The SSD is non-volatile and large amounts of cache items may be transferred to the SSD as an extension of the adapter memory. The cache write may be delayed and subsequently written to a designated address on a RAID drive, freeing the adapter on-board memory and control functions. Further, the size of the SSD allows for large amounts of data staging and storage, permitting device-to-device communications that would reduce the read and write commands between the host, adapter and drives.Type: GrantFiled: November 3, 2000Date of Patent: October 15, 2002Assignee: International Business Machines CorporationInventors: Pat Allen Buckland, Ian David Judd, Gary Robert Lyons, Renato John Recio, Michael Francis Scully
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Publication number: 20020065998Abstract: A method and system for managing data in a data processing system are disclosed. Initially, data is stored in a first portion of the main memory of the system. Responsive to storing the data in the first portion of main memory, information is then stored in a second portion of the main memory. The information stored in the second portion of main memory is indicative of the data stored in the first portion. In an embodiment in which the data processing system is implemented as a multi-node system such as a NUMA system, the first portion of the main memory is in the main memory of a first node of system and the second portion of the main memory is in the main memory of a second node of the system. In one embodiment, storing information in the second portion of the main memory is achieved by storing a copy of the data in the second portion. If a fault in the first portion of the main memory is detected, the information in the second main memory portion is retrieved and stored to a persistent storage device.Type: ApplicationFiled: November 30, 2000Publication date: May 30, 2002Applicant: International Business Machines CorporationInventor: Pat Allen Buckland