Abstract: A method of creating a layout geometry for a multilayer printed circuit board is described. The method involves identifying a signal trace connected to a connector pin via. A antipad is selected for use in conjunction with the connector pin via, where the antipad is of a size selected to prevent interference with said signal trace.

Abstract: A method of creating a layout geometry for a multilayer printed circuit board is described. The method involves identifying a signal trace connected to a connector pin via. A antipad is selected for use in conjunction with the connector pin via, where the antipad is of a size selected to prevent interference with said signal trace.

Abstract: An apparatus and method for a printed circuit board (PCB) for reducing capacitance loading of through-holes. The PCB includes a first electrically conductive via for connecting to the PCB a pin from a connector through a top layer of the PCB. The PCB comprises multiple layers that are electrically isolated from the first electrically conductive via. In addition, the connector provides an electrical signal through the pin that is electrically conductive. The PCB includes a second electrically conductive via that is proximate to the first electrically conductive via. The second electrically conductive via is electrically coupled to one of the multiple layers of the PCB. A trace electrically couples the first electrically conductive via to the second electrically conductive via on a bottom layer of the PCB. The trace allows the pin to be electrically coupled to one of the multiple layers of the PCB.