Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for drone-based administration of remotely located devices. One such method comprises deploying an unmanned aerial vehicle from a base station, wherein the base station assigns a maintenance order to the unmanned aerial vehicle for servicing of a remote device, traveling, by the unmanned aerial vehicle, to the location of the remote device, authenticating, by the unmanned aerial vehicle, a valid identification of the remote device; upon the remote device being authenticated by the unmanned aerial vehicle, servicing the remote device by at least charging a power supply of the remote device and transferring contents of a device log to the unmanned aerial vehicle; and after completing the servicing of the remote device; returning to the base station and transferring contents of the device log to the base station.

Abstract: The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.

Abstract: A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers.

Abstract: A reconfigurable JTAG includes, in part, a core logic, a boundary scan chain cell, one or more reconfigurable blocks (RBs), and a reconfigurable block (RB) programming module. The RBs may include, in part, one or more reconfigurable boundary scan chain blocks (RBB) adapted to couple the boundary scan chain cell to the core logic and to input/output (I/O) ports of the reconfigurable JTAG. The RBs may also include, in part, one or more additional reconfigurable logic (ARL) blocks to provide enhanced logic for locking operations. The RB programmable module may communicate with a memory storing data for configuring the RBBs and ARLs. The RB programming module may configure the RBBs and ARLs based at least in part on the data stored in the memory to disable access to the I/O ports of the JTAG. The RB programming module may configure the RBBs to encrypt the I/O ports in accordance with a cipher algorithm.

Abstract: The present disclosure describes various embodiments of systems, apparatuses, and methods for drone-based administration of remotely located devices. One such method comprises deploying an unmanned aerial vehicle from a base station, wherein the base station assigns a maintenance order to the unmanned aerial vehicle for servicing of a remote device, traveling, by the unmanned aerial vehicle, to the location of the remote device, authenticating, by the unmanned aerial vehicle, a valid identification of the remote device; upon the remote device being authenticated by the unmanned aerial vehicle, servicing the remote device by at least charging a power supply of the remote device and transferring contents of a device log to the unmanned aerial vehicle; and after completing the servicing of the remote device; returning to the base station and transferring contents of the device log to the base station.

Abstract: Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.

Abstract: An integrated circuit includes, in part, a key management unit configured to generate a seeding key during a start-up phase, an encryption module configured to encrypt data using the seeding key and deliver the encrypted data to a second integrated circuit, and an encoder configured to encode the seeding key and deliver the encoded seeding key to the second IC. The second integrated circuit includes, in part, a decoder configured to decode the seeding key. Each of the integrated circuits further includes, in part, a linear-feedback shift register that receives the same clock signals and loads the seeding key.

Abstract: The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.