Patents by Inventor Patrice Couvert

Patrice Couvert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10484514
    Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 19, 2019
    Assignee: KALRAY
    Inventors: Patrice Couvert, Marta Rybczynska, Siméon Marijon, Yann Kalemkarian, Benoît Ganne, Alexandre Blampey
  • Patent number: 9565122
    Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: February 7, 2017
    Assignee: KALRAY
    Inventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin
  • Publication number: 20160134725
    Abstract: The invention relates to a method of processing data frames arriving on a network interface, comprising the following steps implemented in the network interface: storing a set of target positions (tgtPOS), positions in a frame at which are expected at least one parameter characterizing a subframe (ETH_TYPE) and parameters (SRC_IP, DST_IP) characterizing a client-server session; storing an expected value (xpVAL) for the subframe parameter; receiving a current frame and comparing the value (xtVAL) received at the position of the subframe parameter to the expected value; if equal, calculating an index (IDX) from the values received at the positions of the session parameters; and routing the current frame to a processing resource associated with the index.
    Type: Application
    Filed: November 4, 2015
    Publication date: May 12, 2016
    Inventors: Patrice COUVERT, Marta RYBCZYNSKA, Siméon MARIJON, Yann KALEMKARIAN, Benoît GANNE, Alexandre BLAMPEY
  • Publication number: 20140301205
    Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.
    Type: Application
    Filed: October 9, 2012
    Publication date: October 9, 2014
    Inventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin
  • Patent number: 8451283
    Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 28, 2013
    Assignee: STMicroelectronics SA
    Inventors: Patrice Couvert, Anthony Philippe
  • Publication number: 20120256937
    Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. The coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 11, 2012
    Applicant: STMICROELECTRONICS SA
    Inventors: Patrice Couvert, Anthony Philippe
  • Patent number: 8174533
    Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: May 8, 2012
    Assignee: STMicroelectronics SA
    Inventors: Patrice Couvert, Anthony Philippe
  • Patent number: 8046503
    Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: October 25, 2011
    Assignee: STMicroelectronics SA
    Inventors: Patrice Couvert, Xavier Cauchy, Anthony Philippe, Sėbastien Ferroussat
  • Patent number: 7769965
    Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing of data from the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: August 3, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Patrice Couvert, Xavier Cauchy, Anthony Philippe, Sébastien Ferroussat
  • Publication number: 20080228991
    Abstract: A method is provided for managing access to a ring buffer, for at least one data transfer channel for a determined amount of data, with this ring buffer comprising a series of buffer sub-areas spaced apart by a memory address offset and ordered from a first buffer sub-area to a last buffer sub-area. A starting address is initialized from a first register storing the value of the memory address of the first buffer sub-area, and a counter is initialized from a second register storing the value of the number of buffer sub-areas in the buffer. The buffer sub-areas are successively accessed, from the first buffer sub-area to the last buffer sub-area, starting from the starting address and as a function of the memory address offset, on the basis of the value of the counter. The initialization and access steps are repeated such that the determined amount of data is transferred.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 18, 2008
    Applicant: STMICROELECTRONICS SA
    Inventors: Sebastien FERROUSSAT, Patrice COUVERT, Xavier CAUCHY, Anthony PHILIPPE
  • Publication number: 20080024509
    Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.
    Type: Application
    Filed: June 21, 2007
    Publication date: January 31, 2008
    Applicant: STMICROELECTRONICS SA
    Inventors: Patrice Couvert, Anthony Philippe
  • Publication number: 20080005390
    Abstract: A system on chip comprises a CPU, a local memory a data processing module, and a DMA controller. The DMA controller comprises a first interface to handle data transmissions, to and from the local memory, associated with an indication to the local memory of an address in local memory, and is designed to perform data writes and reads in the local memory via this interface. The DMA controller also comprises a second interface, which in response to a command received from the central processing unit, operations for writing and reading data in the local memory via the first interface. The DMA controller also comprises a third interface with the processing module to transmit to it the data read, via the first interface, in the local memory, this transmission not being associated with an indication to the processing module, by the DMA controller, of an address.
    Type: Application
    Filed: May 23, 2007
    Publication date: January 3, 2008
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Patrice Couvert, Xavier Cauchy, Anthony Philippe, Sebastien Ferroussat
  • Publication number: 20070288691
    Abstract: Data stored in a first memory are processed by a processing device comprising a processor, a second memory, and an interface device interfacing the processing device with the first memory. In the interface device, in order to facilitate transfer of data from the first memory where data are stored in a first data format to the second memory where data are stored in a second data format, a first group of data is received from the first memory, with said group ordered into a sequence corresponding to the first data format. Then at least one second group of data is obtained by ordering said data in the first group into a new sequence which is a function of the first and second data formats. The second group of data is stored in the second memory.
    Type: Application
    Filed: March 27, 2007
    Publication date: December 13, 2007
    Applicant: STMicroelectronics S.A.
    Inventors: Patrice Couvert, Xavier Cauchy, Anthony Philippe, Sebastien Ferroussat
  • Patent number: 6460171
    Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: October 1, 2002
    Assignee: STMicroelectronics S.A.
    Inventors: Patrice Couvert, Patrick Correard, Mona Lallement