Abstract: A process for manufacturing an intermetallic contact on the surface of a layer or of a substrate of oriented InxGa1-xAs material, the contact includes an Ni—InGaAs intermetallic compound, the intermetallic compound having a hexagonal crystallographic structure that may have: a first texture or a second texture formed at a second nucleation temperature above the first nucleation temperature; the process comprising the following steps: the production of nomograms defining, for a thickness of Ni deposited, the time to completely consume the initial thickness of Ni as a function of the annealing temperature, the annealing temperature being below the nucleation temperature of the second texture; the localized deposition of Ni on the surface of the InxGa1-xAs material; an annealing step applying the pair of parameters: time required/annealing temperature, deduced from the nomograms, comprising at least one temperature rise step and at least one temperature hold of the final annealing temperature.

Abstract: A process for manufacturing an intermetallic contact on the surface of a layer or of a substrate of oriented InxGa1-xAs material, the contact includes an Ni—InGaAs intermetallic compound, the intermetallic compound having a hexagonal crystallographic structure that may have: a first texture or a second texture formed at a second nucleation temperature above the first nucleation temperature; the process comprising the following steps: the production of nomograms defining, for a thickness of Ni deposited, the time to completely consume the initial thickness of Ni as a function of the annealing temperature, the annealing temperature being below the nucleation temperature of the second texture; the localized deposition of Ni on the surface of the InxGa1-xAs material; an annealing step applying the pair of parameters: time required/annealing temperature, deduced from the nomograms, comprising at least one temperature rise step and at least one temperature hold of the final annealing temperature.

Abstract: A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Abstract: A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Abstract: A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.

Abstract: A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer.

Abstract: A method for measuring the orientation and deviatoric elastic strain of the crystal lattice of grains contained in a sample of polycrystalline material comprising a set of grains (G1, . . . Gi, . . . , Gn) comprises recording a series of Laue patterns and an operation for deinterlacing said Laue patterns, which deinterlacing operation may advantageously be combined with a tomography operation so as to furthermore identify the spatial extent of said grains.