Patents by Inventor Patrice Jaraudias

Patrice Jaraudias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230239180
    Abstract: Examples include a transmitter module, a receiver module and a communication system for exchanging Ethernet Medium Access Control frames on a single M-LVDS line.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 27, 2023
    Applicant: Schneider Electric Industries SAS
    Inventors: Assane Sarr, Maxime Sobocinski, Patrice Jaraudias
  • Publication number: 20230078505
    Abstract: An industrial system for controlling backplane communication, including: a cluster manager including a primary switch linked to a primary control module, at least one Input/Output, I/O, module including a secondary switch linked to a secondary control module, a unidirectional communication line linking the cluster manager to the at least one IO module through passive base plates, wherein the cluster manager includes a transmission port and a reception port on the unidirectional communication line and the at least one Input/Output module includes a reception port on the unidirectional communication line, wherein the primary control module is configured to generate a pulse via the transmission port on the unidirectional communication line, wherein, upon reception of the pulse, the primary control module is configured to create a primary timestamp from a primary clock of the primary switch and the secondary control module is configured to create a secondary timestamp from a secondary clock of the secondary sw
    Type: Application
    Filed: September 1, 2022
    Publication date: March 16, 2023
    Applicant: Schneider Electric Industries SAS
    Inventors: Assane Sarr, Maxime Sobocinski, Patrice Jaraudias
  • Publication number: 20220191150
    Abstract: An industrial system for controlling backplane communication including a cluster manager linked to Input/Output modules via a multipoint low voltage differential signaling, MLVDS, bus through passive base plates. The MLVDS bus contains a transmission line and a reception line for the cluster manager. The transmission line of the MLVDS bus is shared by the Input/Output modules for receiving data transmitted by the cluster manager. The reception line of the MLVDS bus is shared by the Input/Output modules for transmitting data to the cluster manager. The Input/Output modules are synchronized in time with the cluster manager and configured to send data on the reception line of the MLVDS bus at respective scheduled time windows.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 16, 2022
    Applicant: Schneider Electric Industries SAS
    Inventors: Maxime Sobocinski, Philippe Wilhelm, Patrice Jaraudias, Assane Sarr
  • Publication number: 20180349308
    Abstract: A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, thereby providing a single hardware platform that may be used to build various automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc.
    Type: Application
    Filed: August 6, 2018
    Publication date: December 6, 2018
    Applicant: Schneider Electric Industries SAS
    Inventors: Patrice Jaraudias, Jean-Jacques Adragna, Antonio Chauvet, Gary R. Ware
  • Patent number: 10042793
    Abstract: A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a single hardware platform usable to build different automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 7, 2018
    Assignee: Schneider Electric Industries SAS
    Inventors: Patrice Jaraudias, Jean-Jacques Adragna, Antonio Chauvet, Gary R. Ware
  • Patent number: 9703727
    Abstract: A method of managing an electronic microcontroller system, the microcontroller system including: two processors with a first processor configured for execution of a nonsecure application exhibiting a nonguaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application to implement a security function; and a mechanism to access to a shared memory space. The first processor includes a unit for managing the memory configured to implement a write access control, to manage write access to the shared memory space, that is not modifiable when the secure application implements its security function.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: July 11, 2017
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventors: Pascal Chapier, Patrice Jaraudias
  • Publication number: 20160132444
    Abstract: A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a single hardware platform usable to build different automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc.
    Type: Application
    Filed: June 19, 2014
    Publication date: May 12, 2016
    Applicant: Schneider Electric Industries SAS
    Inventors: Patrice JARAUDIAS, Jean-Jacques ADRAGNA
  • Patent number: 9323953
    Abstract: An electronic microcontroller system including: plural processors; at least one interface for exchange with at least one peripheral, the peripheral being user master of the electronic microcontroller system; a mechanism for access to a shared memory space; an interconnection matrix for interconnecting the exchange interface, the processors and the mechanism for access to a shared memory space; a mechanism managing applications involving a guaranteed level of security and integrity and of applications exhibiting a nonguaranteed level of security and integrity. The exchange interface cooperates with a secure isolation cell of the memory situated between the user master peripheral and the interconnection matrix.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 26, 2016
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventor: Patrice Jaraudias
  • Publication number: 20150067773
    Abstract: An electronic microcontroller system including: plural processors; at least one interface for exchange with at least one peripheral, the peripheral being user master of the electronic microcontroller system; a mechanism for access to a shared memory space; an interconnection matrix for interconnecting the exchange interface, the processors and the mechanism for access to a shared memory space; a mechanism managing applications involving a guaranteed level of security and integrity and of applications exhibiting a nonguaranteed level of security and integrity. The exchange interface cooperates with a secure isolation cell of the memory situated between the user master peripheral and the interconnection matrix.
    Type: Application
    Filed: April 4, 2013
    Publication date: March 5, 2015
    Applicant: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventor: Patrice Jaraudias
  • Publication number: 20150032976
    Abstract: A method of managing an electronic microcontroller system, the microcontroller system including: two processors with a first processor configured for execution of a nonsecure application exhibiting a nonguaranteed level of functional security and integrity, and a second processor dedicated to execution of a secure application implementing code and data, and involving a guaranteed level of functional security and integrity, the secure application to implement a security function; and a mechanism to access to a shared memory space. The first processor includes a unit for managing the memory configured to implement a write access control, to manage write access to the shared memory space, that is not modifiable when the secure application implements its security function.
    Type: Application
    Filed: April 4, 2013
    Publication date: January 29, 2015
    Applicant: Schneider Electric Industries SAS
    Inventors: Pascal Chapier, Patrice Jaraudias