Abstract: Interprocessor message communication synchronization apparatus and method for a plurality of processors connected to a system bus where one processor desiring to send a control signal to another processor, broadcasts an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the control signal to be transmitted. Apparatus associated with the receiving processor includes a decoder that responds to the input/output write instruction to enable a register when the address transmitted on the bus matches its address. The enabled register receives the data signals from the bus to set therein the appropriate control signal represented by the data. The stages of the register are connected to the associated control signal inputs of the other processor. In this manner the one processor may transmit a message synchronizing interrupt to the other processor.