Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.

Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.

Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.

Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.

Abstract: Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.

Abstract: A memory system has a memory array divided into a plurality of sub-arrays in which each sub-array has a mutually exclusive power domain, task scheduler circuitry coupled to the memory array, and sub-array power control circuitry coupled to the task scheduler circuitry. A method includes selecting, by the task scheduler circuitry, a task for execution, providing a control signal to the sub-array power control circuitry indicative of a set of sub-arrays to power based on the selected task, and setting a power state of each sub-array, by the sub-array control circuitry, in response to the control signal.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.

Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.

Abstract: Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.

Abstract: An ion sensor for sensing ions in a fluid includes a Metal-Oxide Semiconductor (MOS) varactor formed in and on a semiconductor substrate having a gate dielectric over the semiconductor substrate, a gate over the gate dielectric, a well region in the substrate under the gate dielectric, and source/drain regions in the well region, wherein the well region and the source/drain regions are of a same conductivity type; and a sense electrode coupled to the MOS varactor, wherein the capacitance of the gate dielectric of the varactor changes when the sense electrode interacts with ions in the fluid. Alternatively, resistance of the well region changes when the sense electrode interacts with ions in the fluid, affecting a change in a quality factor of an inductor.

Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.

Abstract: A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. At least one of the body region and the device isolating region includes a plurality of peripheral, constituent regions disposed along a lateral periphery of the active area, each peripheral, constituent region defining a non-uniform spacing between the device isolating region and the body region. The non-uniform spacing at a respective peripheral region of the plurality of peripheral, constituent regions establishes a first breakdown voltage lower than a second breakdown voltage in the conduction path.

Abstract: Semiconductor devices and related electrostatic discharge (ESD) protection methods are provided. An exemplary semiconductor device includes an interface for a signal and a multi-triggered protection arrangement coupled between the interface and a reference node to initiate discharge of the signal between the interface and the reference node based on any one of a plurality of different characteristics of the signal. Discharge of the signal at the interface is initiated based on a first characteristic of the signal, and thereafter, the discharge of the signal at the interface is maintained based on another characteristic of the signal.