Patents by Inventor Patrice Parris
Patrice Parris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9978689Abstract: An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.Type: GrantFiled: December 18, 2013Date of Patent: May 22, 2018Assignee: NXP USA, INC.Inventors: Md M. Hoque, Patrice Parris, Weize Chen, Richard De Souza
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Publication number: 20150171018Abstract: An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: MD M. HOQUE, PATRICE PARRIS, WEIZE CHEN, RICHARD DE SOUZA
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Publication number: 20070158777Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).Type: ApplicationFiled: March 21, 2007Publication date: July 12, 2007Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Edouard de Fresart, Richard De Souza, Xin Lin, Jennifer Morrison, Patrice Parris, Moaniss Zitouni
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Publication number: 20060292755Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Inventors: Patrice Parris, Weize Chen, John McKenna, Jennifer Morrison, Moaniss Zitouni, Richard De Souza
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Publication number: 20060249751Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).Type: ApplicationFiled: May 6, 2005Publication date: November 9, 2006Inventors: Edouard de Fresart, Richard De Souza, Xin Lin, Jennifer Morrison, Patrice Parris, Moaniss Zitouni
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Publication number: 20060223168Abstract: A device for analyzing a fluid sample is provided. The device includes a substrate, a trench formed in said substrate, and a processor. The trench includes a channel, a sample chamber, and a reagent chamber, each in fluid communication with each another. The sample chamber is configured to receive the fluid sample. The processor is integrally formed in the substrate and is in communication with the trench. The processor is configured to analyze the fluid sample. Methods for manufacturing the device are also provided.Type: ApplicationFiled: March 31, 2005Publication date: October 5, 2006Inventor: Patrice Parris
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Patent number: 7074681Abstract: A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.Type: GrantFiled: July 7, 2003Date of Patent: July 11, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Edouard D. de Fresart, Patrice Parris, Richard Joseph De Souza
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Publication number: 20060134862Abstract: A non-volatile memory bitcell structure is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor having a first capacitance value includes a first top plate, a first bottom plate, and a first dielectric disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor having a second capacitance value includes a second top plate, a second bottom plate, and a second dielectric disposed in-between the second top plate and the second bottom plate. An element of the first MIM capacitor is electrically coupled in common with an element of the second MIM capacitor. In addition, the first capacitance value is greater than the second capacitance value.Type: ApplicationFiled: December 17, 2004Publication date: June 22, 2006Inventors: Patrice Parris, Edouard de Fresart, Richard De Souza, Jennifer Morrison
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Publication number: 20060043479Abstract: A semiconductor MOSFET device (70, 100), and method of fabricating the device, including a shielding structure (86, 210) for decreasing the gate-drain capacitance (CGD) without simultaneously increasing the gate resistance or the total device ON-state resistance (RDSON). The shielding structure (86, 210) is formed between a drain region (76, 106) and an active gate electrode (88, 118) in the form of a separate dummy gate (87) or a trench (212) having a material (214) formed therein. The shielding structure (86, 210) forms a capacitance “shield” between the gate (88, 118) and drain region (76, 106). The MOSFET device (70, 100) further includes a semiconductor material (74, 104) defining therein a drain region (76, 106), at least one body region (78, 108) formed in the semiconductor material (74, 104), at least one source region (80, 110) formed in each body region (78, 108), and an active gate electrode (88, 118) formed over the semiconductor material (74, 104).Type: ApplicationFiled: September 2, 2004Publication date: March 2, 2006Inventors: Patrice Parris, Edouard de Fresart
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Patent number: 6828650Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.Type: GrantFiled: May 31, 2002Date of Patent: December 7, 2004Assignee: Motorola, Inc.Inventors: Edouard de Frésart, Patrice Parris, Richard J De Souza, Jennifer H. Morrison, Moaniss Zitouni, Xin Lin
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Patent number: 6787858Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.Type: GrantFiled: October 16, 2002Date of Patent: September 7, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Moaniss Zitouni, Edouard D. de Frésart, Richard J. De Souza, Xin Lin, Jennifer H. Morrison, Patrice Parris
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Patent number: 6747332Abstract: A semiconductor component includes a semiconductor substrate (310) having a first conductivity type, a first semiconductor device (320) at least in a first portion of the semiconductor substrate, and a second semiconductor device (330, 310) at least in a second portion of the semiconductor substrate. The first semiconductor device includes a first electrode region (321), a second electrode region (322), a body region (323), and an isolation region (324) in the first portion of the semiconductor substrate. The body region has the first conductivity type, and the first electrode region, the second electrode region, and the isolation region have a second conductivity type. The second electrode region has a different doping concentration than the first electrode region, and the body region is isolated from the second portion of the semiconductor substrate by the isolation region and the first electrode region.Type: GrantFiled: April 1, 2002Date of Patent: June 8, 2004Assignee: Motorola, Inc.Inventors: Edouard de Frésart, Patrice Parris, Pak Tam
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Publication number: 20040097019Abstract: A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.Type: ApplicationFiled: July 7, 2003Publication date: May 20, 2004Inventors: Edouard D. de Fresart, Patrice Parris, Richard Joseph De Souza
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Publication number: 20040075144Abstract: A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Applicant: Motorola, Inc.Inventors: Moaniss Zitouni, Edouard D. de Fresart, Richard J. De Souza, Xin Lin, Jennifer H. Morrison, Patrice Parris
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Publication number: 20030222329Abstract: A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Applicant: Motorola, Inc.Inventors: Edouard de Fresart, Patrice Parris, Richard J De Souza, Jennifer H. Morrison, Moaniss Zitouni, Xin Lin
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Publication number: 20030183899Abstract: A semiconductor component includes a semiconductor substrate (310) having a first conductivity type, a first semiconductor device (320) at least in a first portion of the semiconductor substrate, and a second semiconductor device (330, 310) at least in a second portion of the semiconductor substrate. The first semiconductor device includes a first electrode region (321), a second electrode region (322), a body region (323), and an isolation region (324) in the first portion of the semiconductor substrate. The body region has the first conductivity type, and the first electrode region, the second electrode region, and the isolation region have a second conductivity type. The second electrode region has a different doping concentration than the first electrode region, and the body region is isolated from the second portion of the semiconductor substrate by the isolation region and the first electrode region.Type: ApplicationFiled: April 1, 2002Publication date: October 2, 2003Applicant: Motorola, Inc.Inventors: Edouard de Fresart, Patrice Parris, Pak Tam
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Publication number: 20030001216Abstract: A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.Type: ApplicationFiled: June 27, 2001Publication date: January 2, 2003Applicant: Motorola, Inc.Inventors: Edouard D. de Fresart, Patrice Parris, Richard Joseph De Souza
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Patent number: 6498066Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines one each connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.Type: GrantFiled: December 4, 2001Date of Patent: December 24, 2002Assignee: Motorola, Inc.Inventors: Patrice Parris, Bruce L. Morton, Walter J. Ciosek, Mark Aurora, Robert Smith
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Patent number: 6383885Abstract: A bipolar transistor (10) in an IC includes a semiconductor wafer defining a collector area (14) with a first conductivity type, a base area (20) with a second conductivity type formed in the collector area (14), and an emitter formed in the base area. A field oxide is positioned on the surface of the semiconductor wafer surrounding the emitter (30) and substantially covering the base area (20) and an implant of the second conductivity type is positioned in the base area (20) between and spaced from the emitter (30) and the outer periphery of the base area (20). The implant further has a heavier concentration of the second conductivity type than the base area to compensate for loss of the second conductivity type under the field oxide and to separate the transistor current path from the breakdown path, which improves the collector to emitter breakdown voltage (BVCEO) while still maintaining a high beta.Type: GrantFiled: October 27, 1999Date of Patent: May 7, 2002Assignee: Motorola, Inc.Inventors: Vasudev Venkatesan, Patrice Parris
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Publication number: 20020042182Abstract: A ROM embedded in a multi-layered integrated circuit includes rows of transistor memory cells. For reduced area, each transistor in a row optionally shares a terminal with an adjacent transistor in the row, whereby adjacent transistors share one of a source and a drain. A plurality of contact lines a connected to each common terminal, serve as address terminals for cells. A plurality of metal layers are connected to the other of the drain or source terminals by filled vias and include a final metal layer defining a metal pad for each of the other terminals. Filled vias couple selected metal pads to selected signal lines to provide “1” outputs from selected cells and signal lines which are not coupled by filled vias to the metal pads provide “0” outputs from selected cells.Type: ApplicationFiled: December 4, 2001Publication date: April 11, 2002Inventors: Patrice Parris, Bruce L. Morton, Walter J. Ciosek, Mark Aurora, Robert Smith