Abstract: This transmission network for transmitting information, of the type comprising at least two associated loops (2, 3) for transmitting information, in each of which functional nodes (4, 5) are integrated, each comprising at least one distribution module for distributing messages (6, 7) between the input and output ports of the node and at least one network interface module (8, 9) associated with this distribution module, is characterised in that the network interface modules (8, 9) of at least certain of the nodes of at least one of the loops (2, 3) are connected to the distribution modules (6, 7) for distributing the nodes of at least one other loop.

Abstract: A data transmission architecture, in particular for use in on-board avionics is disclosed. The data transmission architecture includes at least one main data transmission network with integrated functional nodes for connecting a plurality of peripheral data transmission networks to the main network, in order to provide data transmission between the networks. The data transmission architecture also includes a direct connection of peripheral networks to one another so as to allow the transmission of data directly between the peripheral networks without passing through the main network. The main network includes a plurality of associated sub-networks.

Abstract: A data transmission architecture, in particular for use in on-board avionics is disclosed. The data transmission architecture includes at least one main data transmission network with integrated functional nodes for connecting peripheral connecting networks in a data transmission loop to the main network, in order to provide data transmission between the networks.

Abstract: This multi-core processor system for processing information, of the kind including a data exchange engine (2) associated with multiple users (3) of shared resources (4), is characterized in that it includes means for controlling data exchanges in the processor, associated with each user (3), with the exchange engine (2) and with the shared resources (4) and defining at the processor, a data exchange law determined according to a defined space-time mapping, a giving the possibility of obtaining predictable operating performances of this processor.

Abstract: The invention relates to a message exchange controller structure (1) comprising means (3) forming a message exchange controller, associated with a member (4) forming a storage/exchange buffer, a member (5) forming interfaces for multiple connections to several message production/consumption units, and a member (6) forming interfaces for connecting to several external buses; which is characterized in that the means exchange controller-forming means (3) are able to recover redundant messages from external buses, store those messages in the storage/exchange buffer-forming member (4), recover those messages from the storage/exchange buffer-forming member (4), and process those messages so as to generate a resultant message (MF), to send it to at least one consumption unit.

Abstract: This network comprising functional nodes connected in series by information transmission means, in which the information assumes the form of discrete messages propagating from node to node in the network, is characterized in that the information transmission means between the nodes are bidirectional so as to allow information to propagate in both directions of flow of the network, and each node includes at least one first and one second associated port, for information input/output, connected to adjacent nodes by corresponding information transmission means and the operation of which is controlled exclusively and sequentially, by communication automaton means, between an operating mode for the asynchronous reception of information from its adjacent nodes and an operating mode for the synchronous transmission of information to the nodes adjacent thereto, and in that the communication automaton means are suitable for switching the associated ports of the node from their reception mode of operation to their tran

Abstract: A functional node for an information transmission network and corresponding network are disclosed. In one aspect, the functional node includes at least one module for distributing messages between input and output ports. The distribution module includes at least one combination of at least three ports, including a first input port connected to a second output port by a first capability for unconditionally propagating messages, not depending on the messages. The first and/or second ports are connected to a third port by a second capability for conditionally propagating messages, depending on the messages.

Abstract: A network having a plurality of electronic equipments and a plurality of network nodes is disclosed. The nodes are connected and form a reference ring, according to which ring the nodes are ordered by successive ranks. Each node is connected by a direct receiving connection to an upstream node and via a direct transmission connection to a downstream node. The network is adapted to tolerate a number of network node breakdowns, n being greater than 1. Each node is connected by a direct receiving connection to all of the other nodes placed, in the reference ring, up to: 2 ranks downstream and 1 rank upstream or 1 rank downstream and 2 ranks upstream if n is 2; n?1 ranks downstream and n?1 ranks upstream, if n is odd; or n?1 ranks downstream and n?2 ranks upstream, or n?2 ranks downstream and n?1 ranks upstream, if n is even and greater than 2.

Abstract: This generic and multi-role data and communication exchange controller structure is characterized in that it assumes the form of a single component further including means forming a generic data and communication exchange controller, associated with at least a means forming a data storage/exchange buffer; a means forming multiple connection interfaces to several data production/consumption units, one connection interface being associated with one data production/consumption unit; and a means forming multiple connection interfaces with several external data communication buses, one connection interface being associated with one external data communication bus.

Abstract: A network having a plurality of electronic equipments and a plurality of network nodes is disclosed. The nodes are connected and form a reference ring, according to which ring the nodes are ordered by successive ranks. Each node is connected by a direct receiving connection to an upstream node and via a direct transmission connection to a downstream node. The network is adapted to tolerate a number of network node breakdowns, n being greater than 1. Each node is connected by a direct receiving connection to all of the other nodes placed, in the reference ring, up to: 2 ranks downstream and 1 rank upstream or 1 rank downstream and 2 ranks upstream if n is 2; n-1 ranks downstream and n-1 ranks upstream, if n is odd; or n-1 ranks downstream and n-2 ranks upstream, or n-2 ranks downstream and n-1 ranks upstream, if n is even and greater than 2.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: The present invention relates to computers, the undetected errors of which have a very low rate of occurrence (approximately 10?9 per time unit). This relates in particular to the embedded computers on aircraft that run critical applications such as the automatic pilot, flight management, fuel management or terrain collision prevention. Two or more computation lanes or sections are provided and the exchanges are authorized either on the production or on the consumption of the data by each of the lanes. It is also possible to provide a predefined authorization cycle. The authorization to transfer the datum is given according to a binary comparison logic in the case of two lanes. In the case of more than two lanes, the authorization can be given either by a binary comparison logic or by a majority logic depending on whether the integrity or the availability of the computation system is prioritized.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: Fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device is disclosed. Global scheduling of the real-time computer platform in the form of minor and major cycles is provided in order to reduce latency during sensor acquisition. The associated calculation and preparation of output to the actuator is provided in an integrated modular avionic (IMA) architecture. To achieve the foregoing, a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner is provided.

Abstract: A multichannel digital switching unit including a connection interface between circuits that provides the physical links to a transmitting environment defining the ports and a processing unit that switches multi-field data frames between the different ports. A frame monitoring device include a probe module that is selectively linked to the connection interface and a surveillance module that analyzes contents of at least a part of each data frame processed by the probe and generates a warning signal when the part that is analyzed fails to fulfil a chosen criterion.

Abstract: The field of the invention is that of fiber-optic communication devices known as transceivers, used in the aeronautical field for ensuring that on-board electronic computers can converse with one another, or in civil telecommunication. The subject of the invention is a single-channel transceiver comprising essentially a transmitting optoelectronic part, a receiving optoelectronic part, and a specific optical configuration for transmitting and receiving optical signals on a single optical port in real time and using the same wavelength. The optical architectures according to the invention include no semireflecting components, thus making it possible to reduce light energy losses at transmission and reception of the optical signals. These transceivers are particularly well suited for the construction of single-fiber full-duplex optical communication networks allowing simultaneous transmission and reception of signals.

Abstract: The field of the invention is that of fiber-optic communication devices known as transceivers, used in the aeronautical field for ensuring that on-board electronic computers can converse with one another, or in civil telecommunication. The subject of the invention is a single-channel transceiver comprising essentially a transmitting optoelectronic part, a receiving optoelectronic part, and a specific optical configuration for transmitting and receiving optical signals on a single optical port in real time and using the same wavelength. The optical architectures according to the invention include no semireflecting components, thus making it possible to reduce light energy losses at transmission and reception of the optical signals. These transceivers are particularly well suited for the construction of single-fiber full-duplex optical communication networks allowing simultaneous transmission and reception of signals.

Abstract: The management process of the invention is in particular intended for the temporal management of an ARINC 629 bus for avionics rigs, and it is characterized in that the rigs to which new information is not available or to which only inconsistent information is available are made to send substituted information (WS(2), WS(3)) furnished with characteristic identifications (S1, S2) at the send instants (TA) which are assigned thereto.

Abstract: The invention enables fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device. It provides global scheduling of the real-time computer platform in the form of minor and major cycles in order to reduce latency during sensor acquisition, the associated calculation and preparation of output to the actuator in an integrated modular avionic (IMA) architecture. In order to do this, it uses a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner.

Abstract: A structure to connect a plurality of electronic devices to an ARINC type external bus including a local bus with a sufficiently small length to overcome a phenomena of attenuation and propagation time, a connection channel for connection to the local bus for each of the devices located in one and the same zone, and at least one connection channel for the connection of the local bus to the external bus.