Patents by Inventor Patrice Woodward
Patrice Woodward has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10635615Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.Type: GrantFiled: January 25, 2019Date of Patent: April 28, 2020Assignee: Infineon Technologies AGInventors: Simon Cottam, Patrice Woodward
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Publication number: 20190155775Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.Type: ApplicationFiled: January 25, 2019Publication date: May 23, 2019Inventors: Simon Cottam, Patrice Woodward
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Patent number: 10191871Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.Type: GrantFiled: June 20, 2017Date of Patent: January 29, 2019Assignee: Infineon Technologies AGInventors: Simon Cottam, Patrice Woodward
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Publication number: 20180365181Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Simon Cottam, Patrice Woodward
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Patent number: 8832376Abstract: One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and a cache controller. The SRAM memory device includes a cache data section and a cache tag section. The cache data section includes data entries and the tag section includes tag entries associated with the data entries. The tag entries include memory addresses that correspond to the data entries. The lookup buffer includes lookup entries associated with at least a portion of the data entries. The number of lookup entries is less than the number of tag entries. The cache controller is configured to perform a speculative read of the cache data section and a cache check of the lookup buffer simultaneously or in a single cycle.Type: GrantFiled: March 16, 2012Date of Patent: September 9, 2014Assignee: Infineon Technologies AGInventor: Patrice Woodward
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Publication number: 20130246696Abstract: One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and a cache controller. The SRAM memory device includes a cache data section and a cache tag section. The cache data section includes data entries and the tag section includes tag entries associated with the data entries. The tag entries include memory addresses that correspond to the data entries. The lookup buffer includes lookup entries associated with at least a portion of the data entries. The number of lookup entries is less than the number of tag entries. The cache controller is configured to perform a speculative read of the cache data section and a cache check of the lookup buffer simultaneously or in a single cycle.Type: ApplicationFiled: March 16, 2012Publication date: September 19, 2013Applicant: Infineon Technologies AGInventor: Patrice Woodward
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Patent number: 8458761Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.Type: GrantFiled: June 11, 2002Date of Patent: June 4, 2013Assignee: STMicroelectronics LimitedInventors: Rodrigo Cordero, Patrice Woodward
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Patent number: 7839937Abstract: Circuitry for processing data includes a plurality of filters arranged in parallel. Input data is stored. The input data is applied to the plurality of filters to provide at least two parallel results. An operation is carried out with respect to the results.Type: GrantFiled: June 11, 2002Date of Patent: November 23, 2010Assignee: STMicroelectronics LimitedInventors: Rodrigo Cordero, Patrice Woodward
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Publication number: 20030076856Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.Type: ApplicationFiled: June 11, 2002Publication date: April 24, 2003Applicant: STMicroelectronics LimitedInventors: Rodrigo Cordero, Patrice Woodward
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Publication number: 20020186775Abstract: The invention relates to circuitry for processing data. The circuitry comprises a plurality of filters arranged in parallel and means for storing input data. The input data is applied to the plurality of filters to provide at least two parallel results and means for carrying out an operation with respect to the results.Type: ApplicationFiled: June 11, 2002Publication date: December 12, 2002Inventors: Rodrigo Cordero, Patrice Woodward
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Patent number: 6275535Abstract: A method and device decode a compressed image, and in particular, an image compressed according to the MPEG standards, especially a bidirectional image. To perform two successive decodings of a bidirectional image, the address of the data packet containing the start-of-image identifier of the bidirectional image is tagged, and the temporal reference of this image is stored. After the first decoding, the stored address of the memory is again pointed to and a second decoding is performed after a new detection of the temporal reference of the image.Type: GrantFiled: June 2, 1999Date of Patent: August 14, 2001Assignee: STMicroelectronics S.A.Inventors: Richard Bramley, Patrice Woodward