Patents by Inventor Patricia A. Thaler

Patricia A. Thaler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060098683
    Abstract: A data communication device configured to communicate with a link partner is provided. The data communication device comprises a port coupled to link partner and an auto-negotiation system configured to generate a first differential Manchester signal that comprises information that identifies at least one mode of operation of the data communication device and configured to transmit the first differential Manchester signal to the link partner using the port.
    Type: Application
    Filed: November 10, 2004
    Publication date: May 11, 2006
    Inventor: Patricia Thaler
  • Patent number: 7016971
    Abstract: A distributed computer system includes links and routing devices coupled between the links and routing frames between the links. Each of the routing devices includes a congestion control mechanism for detecting congestion at the routing device and responding to detected congestion by gradually reducing an injection rate of frames routed from the routing device.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: March 21, 2006
    Assignees: Hewlett-Packard Company, IBM Corporation, Compaq Computer Corporation, Adaptec, Inc.
    Inventors: Renato J. Recio, David J. Garcia, Michael R. Krause, Patricia A. Thaler, John C. Krause
  • Patent number: 6904558
    Abstract: Methods for adjusting an m-bit CRC of sub-messages are provided. Such adjustments enable the computation of the CRC of a message by XORing the partial or incremental CRCs of composite sub-messages corresponding to the sub-messages. In a first method, the contents of an m-bit memory location are field squared and stepped to the next state as determined by the Galois field generated by the CRC generating polynomial to adjust the m-bit CRC. In a second method, the partial m-bit CRC of a sub-message is calculated according to CRC generating polynomial, P(x). A variable Y is calculated using a lookup table, where Y=xn modulo P(x). The partial m-bit CRC and Y are multiplied together and divided by P(x). The remainder of the division forms the adjusted m-bit CRC.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: June 7, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Vicente V. Cavanna, Patricia A. Thaler
  • Patent number: 6862701
    Abstract: Self testing of a data communication system that includes a presettable scrambler and a complementary presettable descrambler is performed by presetting the presettable scrambler to a preset state. A seed payload field is scrambled using the presettable scrambler to generate fields of a test sequence. The fields of the test sequence are transmitted and corresponding received test sequence fields are received. The received test sequence fields are descrambled using the presettable descrambler to generate respective recovered test sequence fields. Differences between the recovered test sequence fields and the seed payload field are then detected as errors. In an embodiment, the seed payload field and the preset state of the presettable scrambler are chosen to generate a test sequence that imposes a known stress, such as a given run length, to the data communication system.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: March 1, 2005
    Assignee: Agilent Technologies, Inc.
    Inventors: Richard C. Walker, Patricia A. Thaler
  • Publication number: 20040250193
    Abstract: A system for computing a CRC value includes at least one memory for storing a data message, a current CRC value, and a plurality of lookup tables. The data message includes a plurality of words, with each word including a plurality of bytes. Each of the lookup tables stores a plurality of multi-byte CRC values. The system includes a processor for processing the message a word at a time. The processor is configured to update the current CRC value during processing each word based on an XOR of the word and the current CRC value, and based on a multi-byte CRC value retrieved from each one of the lookup tables.
    Type: Application
    Filed: June 6, 2003
    Publication date: December 9, 2004
    Inventors: Vicente V. Cavanna, Patricia A. Thaler
  • Publication number: 20040059984
    Abstract: A method of generating a CRC for a composite sub-message based on a CRC generating polynomial having at least two factors. The composite sub-message includes sub-message data and a number, n, of trailing zeros. The method includes generating a first remainder based on the sub-message data and a first factor of the CRC generating polynomial. A second remainder is generated based on the sub-message data and a second factor of the CRC generating polynomial. The CRC for the composite sub-message is generated based on adjusted versions of the first and the second remainders.
    Type: Application
    Filed: September 22, 2003
    Publication date: March 25, 2004
    Inventors: Vicente V. Cavanna, Patricia A. Thaler
  • Patent number: 6625159
    Abstract: The present invention provides an improved shared memory switching method in which a guaranteed minimum number of buffers per output port is reserved for each input port. The shared memory may also be optionally divided into reserved and unreserved buffers, with the guaranteed minimum number of buffers being provided from the reserved buffers. The unreserved buffers are available to any port and will handle burst communications and other events that cause a given input port's allocation of reserved buffers to be exhausted. So that bursts are also handled fairly among input ports, additional optional features of the present invention include limiting the number of unreserved buffers that may be consumed by a single input port. For fairness among output ports, method also preferably fairly allocates unreserved buffers among the output ports.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 23, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Bharat K. Singh, Bruce W. Melvin, Patricia A. Thaler
  • Publication number: 20030167440
    Abstract: Methods for adjusting an m-bit CRC of sub-messages are provided. Such adjustments enable the computation of the CRC of a message by XORing the partial or incremental CRCs of composite sub-messages corresponding to the sub-messages. In a first method, the contents of an m-bit memory location are field squared and stepped to the next state as determined by the Galois field generated by the CRC generating polynomial to adjust the m-bit CRC. In a second method, the partial m-bit CRC of a sub-message is calculated according to CRC generating polynomial, P(x). A variable Y is calculated using a lookup table, where Y=xn modulo P(x). The partial m-bit CRC and Y are multiplied together and divided by P(x). The remainder of the division forms the adjusted m-bit CRC.
    Type: Application
    Filed: February 22, 2002
    Publication date: September 4, 2003
    Inventors: Vicente V. Cavanna, Patricia A. Thaler
  • Publication number: 20020129307
    Abstract: Self testing of a data communication system that includes a presettable scrambler and a complementary presettable descrambler is performed by presetting the presettable scrambler to a preset state. A seed payload field is scrambled using the presettable scrambler to generate fields of a test sequence. The fields of the test sequence are transmitted and corresponding received test sequence fields are received. The received test sequence fields are descrambled using the presettable descrambler to generate respective recovered test sequence fields. Differences between the recovered test sequence fields and the seed payload field are then detected as errors. A data communication system having a built-in self-test facility comprises a seed payload field source, a presettable scrambler, a presettable descrambler and an error detector. The presettable scrambler includes an input connected to the seed payload field source and an output coupled to a data transmission medium.
    Type: Application
    Filed: March 6, 2001
    Publication date: September 12, 2002
    Inventors: Richard C. Walker, Patricia A. Thaler
  • Patent number: 6320870
    Abstract: A method and apparatus provides improved flow control on a switched CSMA/CD network where the network implements the BLAM protocol by taking advantage of the fact that a switch on the network may trigger a node to transmit immediately when buffer space becomes available. In such case, the switch then sends a packet to a port that it was previously holding off with collisions, where the packet may be self-addressed or may sent to a null address so that it is not received by any node attached to that port. Such transmission then causes a backoff to be reset to zero, and the node begins transmitting immediately. Alternatively, where a switch has been holding off several ports, it is possible to allow trigger packets from each port in turn as buffer space becomes available.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: November 20, 2001
    Assignee: Hewlett-Packard Company
    Inventor: Patricia A. Thaler
  • Patent number: 6289066
    Abstract: A method and apparatus is provided that solves the problem of data overrun and underrun, for example in a system that exchanges data using the Gigabit Ethernet protocol. A single 8-bit data path is provided as output and the main protocol state machines are kept running in the clock domain of the rest of the circuit, after an elasticity FIFO, so that no additional synchronization is necessary. The invention makes no demands upon the receive clock other than those specified in the relevant standard for duty cycle and accuracy. The invention correctly combines the two effective data streams back into a single data stream, only modifying the FIFO when it is acceptable to do so, and in a way that does not corrupt data packets passing through the FIFO. By providing a minimal set of logic running in the receive clock domain, it is possible to simplify the design of the main protocol state machines. Only a very small portion of the design must be aware of the dual-clock nature of the physical interface.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: September 11, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Bruce E. LaVigne, Patricia A. Thaler, Paul O'Connor
  • Patent number: 5469439
    Abstract: A network system includes end nodes which are connected to a plurality of cascaded hubs. A two priority protocol is provided for selecting end nodes to send network packets over the network. When at least one end node in the network system has a high priority network packet to send, each end node with a high priority network packet is acknowledged in turn. Each end node, when acknowledged, sends its high priority network packet through the network. When no end nodes have a high priority network packet, and at least one end node in the network system has a normal priority network packet to send, each end node with a normal priority network packet is acknowledged in turn. This includes a root hub acknowledging in turn each second level hub which is connected to an end node which has a normal priority network packet to send. Each second level hub, when acknowledged, proceeds to acknowledge in turn each end node which is connected to the second level hub and which has a normal priority network packet.
    Type: Grant
    Filed: May 4, 1994
    Date of Patent: November 21, 1995
    Assignee: Hewlett Packard Company
    Inventors: Patricia A. Thaler, Jayant Kadambi, Michael Spratt, Alan R. Albrecht, Steven H. Goody
  • Patent number: 5396503
    Abstract: Data to be communicated over a plurality of channels is divided into blocks (A1,B1,C1,D1,A2,B2, . . . ), and each successive block is transmitted along a different channel (A,B,C,D) on a cyclic basis. A 5-to-6 bit coding scheme is used with some data values having one possible encoding, with three binary ones, and the remainder having two possible encodings, one with two binary ones and the other with four binary ones. To maintain d.c. balance on each channel, two-ones and four-ones encodings are used alternately for successive occurrences on a channel of any data value having dual encodings. To assist detection of single-bit errors affecting the encoded data, a delimiter having one of two possible values is sent after the final block on each channel; this delimiter value is chosen in accordance with which encoding would have been selected if another dual-encoding data value had occurred on that channel.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: March 7, 1995
    Assignee: Hewlett-Packard Company
    Inventors: Patricia A. Thaler, Jonathan Jedwab