Patents by Inventor Patricia B. Smith

Patricia B. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086240
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for allocating computing resources. In one aspect, a method includes receiving intent data specifying one or more computing services to be hosted by a computing network, requested characteristics of computing resources for use in hosting the computing service, and a priority value for each requested characteristic. A budget constraint is identified for each computing service. Available resources data is identified that specifies a set of available computing resources. A resource allocation problem for allocating computing resources for the one or more computing resources is generated based on the intent data, each budget constraint, and the available resources data. At least a portion of the set of computing resources is allocated for the one or more computing services based on results of evaluating the resource allocation problem to meet a particular resource allocation objective.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Google LLC
    Inventors: David J. Helstroom, Patricia Weir, Cameron Cody Smith, Zachary A. Hirsch, Ulric B. Longyear
  • Patent number: 7344951
    Abstract: According to one embodiment of the invention, a surface preparation method for selective and non-selective epitaxial growth includes providing a substrate having a gate region, a source region, and a drain region, etching a first portion of the source region and the drain region, and removing a second portion of the source region and the drain region by a plasma comprising a noble gas and oxygen.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Majid M. Mansoori, Shirin Siddiqui
  • Patent number: 7253124
    Abstract: A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: August 7, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Patricia B. Smith
  • Patent number: 7232768
    Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: June 19, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Mona M. Eissa
  • Patent number: 7179751
    Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: February 20, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Mona M. Eissa
  • Patent number: 7067441
    Abstract: A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a structure (150) or other means to limit ions from the plasma from reaching the surface of the CDO material (110).
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: June 27, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Phillip D. Matz
  • Patent number: 7001848
    Abstract: Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer 226 of FIG. 2a) on the first conductor (conductor 222 of FIG. 2a), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer 234 of FIG.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: February 21, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, David B. Aldrich, Stephen W. Russell
  • Patent number: 6967173
    Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: November 22, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Mona M. Eissa
  • Patent number: 6958294
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: October 25, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Patent number: 6838300
    Abstract: A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: January 4, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Changming Jin, Phillip D. Matz, Heungsoo Park, Patricia B. Smith, Andrew J. McKerrow
  • Publication number: 20040157450
    Abstract: A structure and a fabrication method for metallurgical connections between solder bumps and contact pads positioned on integrated circuits (IC) having copper interconnecting metallization protected by an overcoat. The structure comprises a portion of the copper metallization exposed by a window in the overcoat, where the exposed copper has a chemically and plasma cleaned surface. A copper layer is directly positioned on the clean copper metallization, and patterned; the resulting metal structure has an electrical (and thermal) conductivity about equal to the conductivity of pure copper. The copper layer overlaps the perimeter of the overcoat window and a copper stud is positioned on said copper layer. Finally, one of the solder bumps is bonded to the copper stud.
    Type: Application
    Filed: February 9, 2004
    Publication date: August 12, 2004
    Inventors: Christo P. Bojkov, Phillip Coffman, Patricia B. Smith
  • Publication number: 20040152296
    Abstract: A method of forming an organosilicate low dielectric constant insulating layer (40) in an integrated circuit, and an integrated circuit structure having such a low-k insulating layer (40), are disclosed. In the case where the low-k dielectric material of the insulating layer (40) comprises an organosilicate glass, subsequent plasma processing has been observed to break bonds between silicon and organic moieties, either by replacing an organic group with a hydroxyl group or with hydrogen, or by leaving a dangling bond. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a silylation agent such as hexamethyldisilazane, which reacts with the damaged molecules, and forms molecules that restore the properties of the film.
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Phillip D. Matz, Patricia B. Smith, Heungsoo Park, Changming Jin, Andrew J. McKerrow
  • Publication number: 20040150012
    Abstract: A method of forming an integrated circuit including an organosilicate low dielectric constant insulating layer (40) formed of a substitution group depleted silicon oxide, such as an organosilicate glass, is disclosed. Subsequent plasma processing has been observed to break bonds in such an insulating layer (40), resulting in molecules at the surface of the film with dangling bonds. Eventually, the damaged insulating layer (40) includes silanol molecules, which results in a degraded film. The disclosed method exposes the damaged insulating layer (40) to a thermally or plasma activated fluorine, hydrogen, or nitrogen, which reacts with the damaged molecules to form a passivated surface for the insulating layer (40).
    Type: Application
    Filed: February 4, 2003
    Publication date: August 5, 2004
    Applicant: Texas Instruments Incorporated
    Inventors: Changming Jin, Phillip D. Matz, Heungsoo Park, Patricia B. Smith, Andrew J. McKerrow
  • Patent number: 6727185
    Abstract: A cleanup process that uses a dilute fluorine in oxygen chemistry in a downstream plasma tool to remove organic and inorganic polymeric residues (116).
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: April 27, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Antonio L. P. Rotondaro, David B. Aldrich, Eric C. Williams
  • Publication number: 20030207563
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: June 9, 2003
    Publication date: November 6, 2003
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20030203642
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: June 9, 2003
    Publication date: October 30, 2003
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Patent number: 6599829
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Grant
    Filed: February 25, 2002
    Date of Patent: July 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20030116845
    Abstract: A structure and a fabrication method for metallurgical connections between solder bumps and contact pads positioned on integrated circuits (IC) having copper interconnecting metallization protected by an overcoat. The structure comprises a portion of the copper metallization exposed by a window in the overcoat, where the exposed copper has a chemically and plasma cleaned surface. A copper layer is directly positioned on the clean copper metallization, and patterned; the resulting metal structure has an electrical (and thermal) conductivity about equal to the conductivity of pure copper. The copper layer overlaps the perimeter of the overcoat window and a copper stud is positioned on said copper layer. Finally, one of the solder bumps is bonded to the copper stud.
    Type: Application
    Filed: February 26, 2002
    Publication date: June 26, 2003
    Inventors: Christo P. Bojkov, Phillip Coffman, Patricia B. Smith
  • Publication number: 20020127840
    Abstract: An embodiment of the instant invention is a method of fabricating an electronic device formed on a semiconductor wafer, the method comprising the steps of: forming a layer of a first material (layer 622 of FIG. 6a) over the substrate; forming a photoresist layer (layer 626 of FIG. 6b) over the layer of the first material; patterning the layer of the first material; removing the photoresist layer after patterning the layer of the first material; and subjecting the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen or deuterium so as to remove residue from the first material. Preferably, the step of removing the photoresist layer is performed by subjecting the semiconductor wafer to the plasma which incorporates a gas which substantially includes hydrogen or deuterium.
    Type: Application
    Filed: February 25, 2002
    Publication date: September 12, 2002
    Inventors: Patricia B. Smith, Guoqiang Xing, David B. Aldrich
  • Publication number: 20020076929
    Abstract: A pre-ECD surface treatment. After forming the barrier material (110) and seed layer (112), the surface of the seed layer (112) is treated with an H2 plasma to remove surface contamination (122), reduce any CuOx (123), and improve wettability. The ECD copper film (124) is then formed over the seed layer (112).
    Type: Application
    Filed: October 4, 2001
    Publication date: June 20, 2002
    Inventors: Jiong-Ping Lu, Patricia B. Smith