Abstract: In a multinode data processing system in which data is transferred, via direct memory access (DMA) or in remote direct memory access (RDMA), from a source node to at least one destination node through communication adapters coupling each node to a network or switch, a method is provided in which interrupt handling is overlapped with data transfer so as to allow interrupt processing overhead to run in parallel at the destination node with the movement of data to provide performance benefits. The method is also applicable to situations involving multiple interrupt levels corresponding to multithreaded handling capabilities.

Abstract: In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism is provided within the realm of Remote Direct Memory Access (RDMA) operations in which DMA operations are present on one side of the transfer but not the other. On the side in which the transfer is not carried out in DMA fashion, transfer processing is carried out under program control; this is in contrast to the transfer on the DMA side which is characteristically carried out in hardware. Usage of these combination processes is useful in programming situations where RDMA is carried out to or from contiguous locations in memory on one side and where memory locations on the other side is noncontiguous. This split mode of transfer is provided both for read and for write operations.

Abstract: A system and method that utilizes a dedicated transmission queue to enable expedited transmission of data messages to adaptive “nearest neighbor” nodes within a cluster. Packet descriptors are pre-fetched by the communications adapter hardware during the transmission of the preceding data element and setup for the next transmission is performed in parallel with the transmission of the preceding data element. Data elements of a fixed length that is equal to the cache line size of the communication hardware can optionally be used to provide optimized transfer between computer memory and communications hardware. The data receiving processing can also be optimized to recognize and handle cache line size data elements.