Patents by Inventor Patricia Maria Sagmeister
Patricia Maria Sagmeister has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10321580Abstract: Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle ? therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.Type: GrantFiled: July 29, 2016Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Ralph Heller, Patricia Maria Sagmeister, Martin Leo Schmatz
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Patent number: 10008474Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.Type: GrantFiled: July 11, 2016Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Thomas J. Brunschwiler, Andreas Christian Doering, Ronald Peter Luijten, Stefano Sergio Oggioni, Patricia Maria Sagmeister, Martin Leo Schmatz
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Publication number: 20180035544Abstract: Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle ? therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Inventors: Ralph HELLER, Patricia Maria SAGMEISTER, Martin Leo SCHMATZ
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Publication number: 20180012864Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Thomas J. BRUNSCHWILER, Andreas Christian DOERING, Ronald Peter LUIJTEN, Stefano Sergio OGGIONI, Patricia Maria SAGMEISTER, Martin Leo SCHMATZ
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Patent number: 8972667Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.Type: GrantFiled: June 27, 2012Date of Patent: March 3, 2015Assignee: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Victoria Caparros Cabezas, Andreas Christian Doering, Patricia Maria Sagmeister
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Patent number: 8424014Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.Type: GrantFiled: February 27, 2009Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Patricia Maria Sagmeister
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Publication number: 20130007398Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.Type: ApplicationFiled: September 5, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Victoria Caparros Cabezas, Andreas Christian Doering, Patricia Maria Sagmeister
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Publication number: 20130007375Abstract: A device with an interconnect having a plurality of memory controllers for connecting the plurality of memory controllers. Each memory controller of the plurality of memory controllers is coupled to an allocated memory for storing data. Further, each memory controller of the plurality of memory controllers has one accelerator of a plurality of accelerators for mutually exchanging data over the interconnect.Type: ApplicationFiled: June 27, 2012Publication date: January 3, 2013Applicant: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Victoria Caparros Cabezas, Andreas Christian Doering, Patricia Maria Sagmeister
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Patent number: 8250304Abstract: A memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache data injection into the particular cache line triggered by a bus-actor.Type: GrantFiled: December 3, 2008Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Patricia Maria Sagmeister
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Patent number: 7990869Abstract: A method for monitoring data congestion in a computer network with multiple nodes and for controlling data transmission in the computer network. The method includes generating a congestion notification by the node which detects a data congestion and transmitting the congestion notification to the data source which is involved in the data congestion. The method also includes generating in the data source a congestion value which indicates how severe the data congestion is, and storing in a worst case array of the data source those congestion values which indicate the most severe data congestions.Type: GrantFiled: November 26, 2008Date of Patent: August 2, 2011Assignee: International Business Machines CorporationInventors: Wolfgang Emil Denzel, Andreas Christian Döring, Maria Gabrani, Mircea Gusat, Patricia Maria Sagmeister, Thomas Schlipf
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Publication number: 20100223624Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.Type: ApplicationFiled: February 27, 2009Publication date: September 2, 2010Applicant: International Business Machines CorporationInventors: Florian Alexander Auernhammer, Patricia Maria Sagmeister
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Patent number: 7613850Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.Type: GrantFiled: December 23, 2008Date of Patent: November 3, 2009Assignee: International Business Machines CorporationInventors: Andreas Christian Doering, Patricia Maria Sagmeister, Jonathan Bruno Rohrer, Silvio Dragone, Rolf Clauberg, Florian Alexander Auernhammer, Maria Gabrani
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Publication number: 20090144505Abstract: The present invention relates to a memory device, in particular, to a memory device comprising a cache memory with a predetermined amount of cache sets, each cache set comprising a predetermined amount of cache lines. Each cache line is operable to indicate a cache data injection into the particular cache line triggered by a bus-actor.Type: ApplicationFiled: December 3, 2008Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Florian Alexander Auemhammer, Patricia Maria Sagmeister
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Publication number: 20090141630Abstract: A method for monitoring data congestion in a computer network with multiple nodes and for controlling data transmission in the computer network. The method includes generating a congestion notification by the node which detects a data congestion and transmitting the congestion notification to the data source which is involved in the data congestion. The method also includes generating in the data source a congestion value which indicates how severe the data congestion is, and storing in a worst case array of the data source those congestion values which indicate the most severe data congestions.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Inventors: Wolfgang Emil Denzel, Andreas Christian Doring, Maria Cabrani, Mircea Gusat, Patricia Maria Sagmeister, Thomas Schlipf
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Publication number: 20080080504Abstract: A method and system for managing flow of a plurality of packets in a lossless communication network interconnected by a plurality of switching-nodes is provided. The method includes creating a plurality of virtual-queues. Each virtual-queue corresponds to an output port of a switching-node. Thereafter, each packet is assigned to a virtual-queue. A packet is assigned to a virtual-queue based on information stored in a header of the packet.Type: ApplicationFiled: September 28, 2006Publication date: April 3, 2008Inventors: Mircea Gusat, Cyriel Johan Agnes Minkenberg, Wolfgang Emil Denzel, Patricia Maria Sagmeister, Andreas Christian Doring, Thomas Schlipf, Maria Gabrani