Patents by Inventor Patricia S. Dupuis
Patricia S. Dupuis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9124361Abstract: Embodiments of the concepts described herein are directed toward a common RF building block in the form of a monolithic assembly for an AESA array featuring a scalable RF design based on 2n:3 combining. The monopulse network building blocks are substantially identical, enabling an interchangeable sub-array architecture that is independent of position in the AESA aperture and receive sum channel sidelobe performance. In one embodiment, a passive Monopulse Beamformer may provide the passive 2n:3 RF coupling/combining network and an active Monopulse Processor may perform amplitude and phase weighting for the combined signals from the Monopulse Beamformer.Type: GrantFiled: October 6, 2011Date of Patent: September 1, 2015Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Tunglin L. Tsai, John B. Francis, Donald A. Bozza, Kathe I. Scott, Patricia S. Dupuis
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Patent number: 9019166Abstract: In one aspect, an active electronically scanned array (AESA) card includes a printed wiring board (PWB) that includes a first set of metal layers used to provide RF signal distribution, a second set of metal layers used to provide digital logical distribution, a third set of metal layers used to provide power distribution and a fourth set of metal layers used to provide RF signal distribution. The PWB comprises at least one transmit/receive (T/R) channel used in an AESA.Type: GrantFiled: November 14, 2011Date of Patent: April 28, 2015Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Patricia S. Dupuis, Craig C. Lemmler, Donald A. Bozza, Kassam K. Bellahrossi, James A. Robbins, John B. Francis
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Patent number: 8981869Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.Type: GrantFiled: January 27, 2010Date of Patent: March 17, 2015Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Publication number: 20130088381Abstract: Embodiments of the concepts described herein are directed toward a common RF building block in the form of a monolithic assembly for an AESA array featuring a scalable RF design based on 2n:3 combining. The monopulse network building blocks are substantially identical, enabling an interchangeable sub-array architecture that is independent of position in the AESA aperture and receive sum channel sidelobe performance. In one embodiment, a passive Monopulse Beamformer may provide the passive 2n:3 RF coupling/combining network and an active Monopulse Processor may perform amplitude and phase weighting for the combined signals from the Monopulse Beamformer.Type: ApplicationFiled: October 6, 2011Publication date: April 11, 2013Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Tunglin L. Tsai, John B. Francis, Donald A. Bozza, Kathe I. Scott, Patricia S. Dupuis
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Publication number: 20120313818Abstract: In one aspect, an active electronically scanned array (AESA) card includes a printed wiring board (PWB) that includes a first set of metal layers used to provide RF signal distribution, a second set of metal layers used to provide digital logical distribution, a third set of metal layers used to provide power distribution and a fourth set of metal layers used to provide RF signal distribution. The PWB comprises at least one transmit/receive (T/R) channel used in an AESA.Type: ApplicationFiled: November 14, 2011Publication date: December 13, 2012Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Patricia S. Dupuis, Craig C. Lemmler, Donald A. Bozza, Kassam K. Bellahrossi, James A. Robbins, John B. Francis
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Patent number: 8279131Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.Type: GrantFiled: June 15, 2009Date of Patent: October 2, 2012Assignee: Raytheon CompanyInventors: Angelo M Puzella, Joseph A. Licciardello, Patricia S. Dupuis, John B. Francis, Kenneth S. Komisarek, Donald A. Bozza, Roberto W. Alm
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Publication number: 20100126010Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.Type: ApplicationFiled: January 27, 2010Publication date: May 27, 2010Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Publication number: 20100066631Abstract: A mixed-signal, multilayer printed wiring board fabricated in a single lamination step is described. The PWB includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the PWB. The PWB includes a number of unit cells with radiating elements and an RF cage disposed around each unit cell to isolate the unit cell. A plurality of flip-chip circuits are disposed on an external surface of the PWB and a heat sink can be disposed over the flip chip components.Type: ApplicationFiled: June 15, 2009Publication date: March 18, 2010Applicant: Raytheon CompanyInventors: Angelo M. Puzella, Joseph A. Licciardello, Patricia S. Dupuis, John B. Francis, Kenneth S. Komisarek, Donald A. Bozza, Roberto W. Alm
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Patent number: 7671696Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.Type: GrantFiled: November 9, 2006Date of Patent: March 2, 2010Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Publication number: 20100033262Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.Type: ApplicationFiled: November 9, 2006Publication date: February 11, 2010Inventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Publication number: 20080074324Abstract: A radiator includes a waveguide having an aperture and a patch antenna disposed in the aperture. In one embodiment, an antenna includes an array of waveguide antenna elements, each element having a cavity, and an array of patch antenna elements including an upper patch element and a lower patch element disposed in the cavity.Type: ApplicationFiled: September 21, 2006Publication date: March 27, 2008Inventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Patent number: 7348932Abstract: A radiator includes a waveguide having an aperture and a patch antenna disposed in the aperture. In one embodiment, an antenna includes an array of waveguide antenna elements, each element having a cavity, and an array of patch antenna elements including an upper patch element and a lower patch element disposed in the cavity.Type: GrantFiled: September 21, 2006Date of Patent: March 25, 2008Assignee: Raytheon CompanyInventors: Angelo M. Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica, John B. Francis, Joseph A. Licciardello
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Patent number: 6731189Abstract: A multi-layer stripline assembly interconnection includes a first stripline sub-assembly having a first surface and a first plurality of vias disposed in the first surface adapted to receive a plurality of solid metal balls. The interconnection further includes a second stripline sub-assembly having a second plurality of vias disposed in the first surface of the second sub-assembly adapted to be aligned with the first plurality of vias. Reflowed solder is wetted to the second plurality of vias and to the corresponding plurality of solid metal balls.Type: GrantFiled: June 27, 2002Date of Patent: May 4, 2004Assignee: Raytheon CompanyInventors: Angelo Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica
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Publication number: 20040000979Abstract: A multi-layer stripline assembly interconnection includes a first stripline sub-assembly having a first surface and a first plurality of vias disposed in the first surface adapted to receive a plurality of solid metal balls. The interconnection further includes a second stripline sub-assembly having a second plurality of vias disposed in the first surface of the second sub-assembly adapted to be aligned with the first plurality of vias. Reflowed solder is wetted to the second plurality of vias and to the corresponding plurality of solid metal balls.Type: ApplicationFiled: June 27, 2002Publication date: January 1, 2004Inventors: Angelo Puzella, Joseph M. Crowder, Patricia S. Dupuis, Michael C. Fallica