Abstract: A method and apparatus for implementation of a pipeline structure for data transfer. A request is received from a first domain to access a second domain during a first clock cycle. A pipeline structure is used to perform at least a portion of the request during a subsequent clock cycle.

Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.

Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.

Abstract: The present invention provides a method and apparatus for inter-domain data transfer. The method includes mapping a memory region of a source device into a central device and mapping a memory region of a target device into the central device. The method further includes transferring data from the mapped memory region of the source device to the mapped memory region of the target device.

Abstract: A system and method are provided for efficient handling of streaming-data in a cache memory system (105) having a cache with several cache-lines (160) capable of storing data. In one aspect, a method is provided for determining before storing data to a cache-line if the storing of data will replace earlier data already stored in cache (135). If the storing of data will replace data in the cache (135), it is determined if the data that will be replaced is streaming-data. If the data to be replaced is not streaming-data, it is stored into victim cache (155). However, if the data to be replaced is streaming-data, it is not stored into the victim cache, thereby improving system efficiency by eliminating the copying of data to be replaced and avoiding replacing other earlier data in victim cache (155) that may be needed in the future.

Abstract: A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested.

Abstract: The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.

Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.

Abstract: The present invention provides a project optimization software tool in which a single window in a graphical user interface serves as a tool for planning future actions, reviewing past actions, organizing meetings and launching executable software tools. A project pathway window supports: 1) the listing and viewing of sequences of pathway steps, which, if accomplished, lead towards a defined project goal, 2) the ability to link software tools to those pathway steps, and launch the software tools for execution, 3) the creation of meeting agendas, each of which may encompass several pathway steps, without demoting the included pathway steps, and 4) the marking of the status of pathway steps.

Abstract: A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.