Abstract: The present invention provides compounds of formula I wherein X, Y, R1-R7 are as defined herein. Compositions containing these compounds, and methods for inhibiting HCV RNA-dependent RNA polymerase and treating hepatitis C and related disorders using these compounds and compositions are also provided.

Abstract: In its many embodiments, the present invention provides a novel class of imidazo[1,2-a]pyrazine compounds as inhibitors of cyclin dependent kinases, methods of preparing such compounds, pharmaceutical compositions containing one or more such compounds, methods of preparing pharmaceutical formulations comprising one or more such compounds, and methods of treatment, prevention, inhibition, or amelioration of one or more diseases associated with the CDKs using such compounds or pharmaceutical compositions.

Abstract: A powertrain control method and strategy for a hybrid electric vehicle is disclosed including establishing electric motor-generator regenerative braking on a first driving axle and engine compression braking for a second driving axle when the vehicle is in a deceleration mode and friction braking the first driving axle when regenerative braking, the friction braking complementing regenerative braking to satisfy a given total braking request.

Abstract: A high tensile strength, highly conductive flexible composite sheet consisting of fibrillated PTFE polymers, performance enhancing dopants, and carbon particles useful in electrochemical devices such as flow through capacitors, capacitive deionization, electronic water purification, fuel cells, capacitors, super-capacitors and a method of preparation. The method consists of mixing the materials and calendering to the desired thickness and strength all at room temperature and leaving the material in a wet state without further drying.

Abstract: A method of obtaining an enantioenriched organic compound comprising the steps of: 1) generating from a starting racemic, non-enantiopure or achiral compound a first mixture comprising at least one fluorous-tagged compound and at least one other non-fluorous tagged compound, at least one of these two compounds being enantioenriched relative to the starting compound; 2) contacting a first non-fluorous phase including the first mixture with a fluorous phase at a first phase interface, the fluorous-tagged compound distributing between the first non-fluorous phase and the fluorous phase; and 3) contacting the fluorous phase with a second non-fluorous phase at a second phase interface. The method further includes the step of having a third compound in the second non-fluorous phase that reacts with the fluorous-tagged compound to produce a second compound and the step of generating the first mixture by chemical or enzymatic kinetic resolution of a racemic or non-enantiopure compound.

Abstract: A semiconductor contact system is formed by inductively coupling an ohmic electrode, such as a metal, to a semiconductor region by means of an intervening diamagnetic boride glass, which necessarily constrains most electric current to prevail along the uniaxial normal to the semiconductor contact. The low permeability of the diamagnetic boride glass results in a low resistance to direct-current electricity along the uniaxial displacement axis of the diamagnetic boride glass. The transient time constant associated with the inductor is generally much smaller than the semiconductor device switching times, with the steady-state current being essentially established by the semiconductor resistance so as to result in an ohmic semiconductor contact void any significant rectification effects. An ohmic contact by means of an inductively-coupled electrode is generally independent of the semiconductor conductivity or ionicity.

Abstract: A film for hermetically passivating monocrystalline silicon includes sequential layers of undoped amorphous silicon, oxygen doped polycrystalline silicon, silicon rich oxynitride, and silicon nitride, and may be overlaid with an organic bulk dielectric such as polyimide. The inorganic film accurately sets the monocrystalline surface Fermi potential, independent of ambient electrical, mechanical, thermal, ionic, and moisture conditions. A method for depositing the amorphous silicon and the oxygen doped polycrystalline silicon layers of the film includes sequentially reacting monosilane in an inert carrier gas, such as helium or argon, and nitrous oxide. The layers are blended by varying the deposition temperature, the nitrous oxide flow rate, the monosilane flow rate, the monosilane dilution, and the inert carrier gas species. The layers are annealed to locally segregate the oxygen, to grow the grains to the proper size, and to set the final recombination velocity of the monocrystalline region.

Abstract: A heterojunction transistor has an acceptor doped superlattice base of sub-micron thickness, a composite emitter with a donor concentration adjacent the base, with a wider bandgap energy than the base, and with a low recombination velocity to minimize minority carrier diffusion and to set the divergence of emitter and base carrier velocities, and a collector configured like the emitter, permitting control and optimization of the cut-in voltage. The method for making the transistor includes forming the base, emitter, and collector by non-compensated, non-planar wafer processing techniques.

Abstract: A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus.

Abstract: A semiconductor contact system controls the boundary recombination velocity and optimizes the semiconductor transport phenomena and includes a microcrystalline layer of doped semiconductor microcrystals surrounded by a semiconductor oxide. The microcrystalline layer is acceptor and oxygen doped to provide unipolar hole transport and donor and oxygen doped to provided unipolar electron transport. The oxygen doping is implanted several atomic layers into the semiconductor to form a gradient between the semiconductor and microcrystalline layer to preserve the semiconductor monocrystalline lattice. The thickness of the microcrystalline film is adjusted to be thick enough to control the effective chemostatic potential terminating the semiconductor and thin enough to enhance the series microcrystalline film resistance.

Abstract: A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Abstract: A passivated dual dielectric gate system compatible with low temperature processing utilizes a dual dielectric system with a silicon dioxide dielectric film or layer at the monocrystalline substrate surface, or termination. The dual dielectric system includes a dielectric film at the substrate surface of thicknesses of from 200 to 1000 .ANG.(or greater ). Respective layers of undoped amorphous silicon and titanium nitride overlie the top of the silicon dioxide and an aluminum gate metal layer overlies the titanium nitride layer. The structure can be patterned by selectively patterning photoresist and a dry or dry/wet etch processses. The structure is patterned and etched as desired.

Abstract: A process, and product made thereby, for bonding two wafers together to form a single wafer with a continuous interface, and for selectively burying a low impedance conductor in the wafer, by providing host and guest wafers having substantially the same crystal orientation and periodicity. A crystalline boundary n-semimetal is formed on the wafers, which are then brought into intimate contact. If desired, a unipolar conductor is fused to one of said wafers. Then, the wafers are exposed to an elevated temperature, or rapid thermal anneal, in an inert ambient, breaking up any native oxides and diffusing any excess oxygen into the wafer lattices. The guest wafer is then mechanically lapped back and chemically etched.A vertical cascode integrated half H-bridge motor driving circuit made in the guest and host wafers has a source transistor in the host wafer with with the wafer substrate forming the collector of the transistor, an isotype acceptor doped Ge.sub.x Si.sub.

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.