Patents by Inventor Patrick A. Kearney

Patrick A. Kearney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8865376
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: October 21, 2014
    Assignees: Sematech, Inc., Intel Corporation
    Inventors: Vibhu Jindal, Frank Goodwin, Patrick A. Kearney, Eric M. Panning
  • Publication number: 20140255828
    Abstract: Methods are provided for fabricating a process structure, such as a mask or mask blank. The methods include, for instance: providing a silicon substrate; forming a multi-layer, extreme ultra-violet lithography (EUVL) structure over the silicon substrate; subsequent to forming the multi-layer EUVL structure over the crystalline substrate, reducing a thickness of the silicon substrate; and attaching a low-thermal-expansion material (LTEM) substrate to one of the multi-layer EUVL structure, or the reduced silicon substrate. In one implementation, the silicon substrate is a silicon wafer with a substantially defect-free surface upon which the multi-layer EUVL structure is formed. The multi-layer EUVL structure may include multiple bi-layers of a first material and a second material, as well as a capping layer, and optionally, an absorber layer, where the absorber layer is patternable to facilitating forming a EUVL mask from the process structure.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicants: INTEL CORPORATION, SEMATECH, INC.
    Inventors: Vibhu JINDAL, Frank GOODWIN, Patrick A. KEARNEY, Eric M. PANNING
  • Patent number: 6554968
    Abstract: A method for producing film thickness control of ion beam sputter deposition films. Great improvements in film thickness control is accomplished by keeping the total current supplied to both the beam and suppressor grids of a radio frequency (RF) in beam source constant, rather than just the current supplied to the beam grid. By controlling both currents, using this method, deposition rates are more stable, and this allows the deposition of layers with extremely well controlled thicknesses to about 0.1%. The method is carried out by calculating deposition rates based on the total of the suppressor and beam currents and maintaining the total current constant by adjusting RF power which gives more consistent values.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: April 29, 2003
    Assignee: The Regents of the University of California
    Inventors: Patrick A. Kearney, Scott C. Burkhart
  • Patent number: 6521897
    Abstract: A collimating grid for an ion source located after the exit grid. The collimating grid collimates the ion beamlets and disallows beam spread and limits the beam divergence during transients and steady state operation. The additional exit or collimating grid prevents beam divergence during turn-on and turn-off and prevents ions from hitting the periphery of the target where there is re-deposited material or from missing the target and hitting the wall of the vessel where there is deposited material, thereby preventing defects from being deposited on a substrate to be coated. Thus, the addition of a collimating grid to an ion source ensures that the ion beam will hit and be confined to a specific target area.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: February 18, 2003
    Assignee: The Regents of the University of California
    Inventors: Walter B. Lindquist, Patrick A. Kearney