Abstract: A system for adjusting a phase angle of a recovered data clock signal from a received data signal includes a plurality of counters and a phase state machine. Each counter within the plurality of counters determines a number of samples having a logical one (1) value within a particular portion of a period of the received data signal. Each counter then compares the number to a predetermined threshold value. Each counter transmits a signal indicating whether the number of samples having a logical one (1) for each portion of received data signal's period is greater than, is less than, or is equal to the predetermined threshold. The phase state machine receives the signals transmitted by each counter and adjusts the phase angle of the recovered data clock signal based on the signals received from each counter.

Abstract: A bit of a data signal is encoded with a value of a transmission clock signal if the bit corresponds to a zero. If the bit corresponds to a one, then the bit is encoded with an inverse of the value of the transmission clock signal. After transmission, the encoded signal is decoded by a counter and a comparator. The counter samples the encoded bit of the data signal into a plurality of sampled signals and inverts a portion of the sampled signals. The counter counts the number of sampled signals corresponding to a particular value such as a one or zero. When most of the sampled signals correspond to the particular value, a comparator outputs a decoded signal having a value corresponding to the particular value. When most of the sampled signals do not correspond to the particular value, the comparator outputs a decoded signal having a value corresponding to an inverse of the particular value.