Abstract: A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align the VCO signal with the delayed input data. The delayed input data is clocked into a flip-flop on the opposite phase of the VCO signal to produce an output signal. In a preferred embodiment the delay of the input data for phase comparison, and the delay of the input data for the output flip-flop can be independently selected.

Abstract: Integrated injection logic circuits and semiconductor devices employing threshold functions. Multiple-collector input transistors have their collectors connected to the bases of one or more output transistors. The output transistors have different weighted levels of injection current. The switching states of the output transistors are functions of the number of and conduction state of input transistors to which the output transistor are connected and to the weight of the injection current associated with the output transistor.

Abstract: In a semiconductor structure, a semiconductor body of one conductivity type having a planar surface and a first region of opposite conductivity formed in said body and extending to said surface. Spaced second, third and fourth regions of one conductivity type are formed in said first region and extend to said surface. Fifth and sixth regions of opposite conductivity are respectively formed entirely within said second and third regions and extend to said surface. In addition a seventh region of one conductivity type may be formed spaced from said second, third and fourth regions and an eighth region of opposite conductivity type formed entirely within said seventh region. A method for forming the semiconductor logic structure is also disclosed.