Abstract: For this system and for this equipment there has been provided a phase alignment device (30) which has an access for input data (50) applied to an access (51) at a rate of a first clock signal, and an access (70) for producing at the rate of a second clock signal applied to an access (71) a justifiable data stream, in which stream bits can be inserted or deleted. The data are written and read in and from a common memory (60) by means of a write counter (55) and a read counter (80), respectively. A comparing element (90) measures the difference of the contents of said counters (55) and (80). With each variation of this difference, intermediate steps are added with the elements (95), (97) and (98), so that the means (92) controlling the justification can be formed by a sigma-delta modulator which has a 0.5 threshold.

Abstract: A frequency synthesizer device has an input port for a digital code which defines the frequency to be synthesized and an accumulator circuit for successively counting the digital codes in the form of numbers in time with signals of an accumulation clock. An accumulation decoder is coupled to the accumulator circuit and supplies accumulation information relating to the counted number in the accumulator circuit. A variable divider circuit is controlled by this accumulation information to supply the synthesized frequency signals based upon the signals of a reference clock.