Patents by Inventor Patrick Ampe

Patrick Ampe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10563397
    Abstract: An improved insulating block that offers great structural strength by having an interconnected block material structure with cavities filled with insulating material. The paths from the front face to the back face of the block through the block material are adapted to ensure an improved thermal insulation of the block, while providing a high load bearing capacity and allowing continuation of longitudinal reinforcement. This results in a block that can be easily manipulated and handled. Furthermore, the invention provides a method of manufacturing and a use of said blocks, and a wall or structure of said blocks.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 18, 2020
    Assignee: UNIVERSITEIT GENT
    Inventors: Leo Van Cauter, Patrick Ampe, Veerle Boel
  • Publication number: 20180298608
    Abstract: An improved insulating block that offers great structural strength by having an interconnected block material structure with cavities filled with insulating material. The paths from the front face to the back face of the block through the block material are adapted to ensure an improved thermal insulation of the block, while providing a high load bearing capacity and allowing continuation of longitudinal reinforcement. This results in a block that can be easily manipulated and handled. Furthermore, the invention provides a method of manufacturing and a use of said blocks, and a wall or structure of said blocks.
    Type: Application
    Filed: October 3, 2016
    Publication date: October 18, 2018
    Inventors: Leo Van Cauter, Patrick Ampe, Veerle BOEL
  • Patent number: 5272391
    Abstract: A synchronizing circuit to synchronize a digital input signal (DIN) with a clock signal (CK1) includes a detection circuit (DC) which checks if a present (SA) sample of a clock signal (CK3) being synchronized with the digital input signal, is equal to the previous (SB) sample, both samples being taken at an interval equal to the period (T) of the clock signal synchronized with the output signal. When the samples differ, the detection circuit generates a phase adjustment signal (CLR), which triggers a phase adjustment circuit (PAC) to ensure a return to synchronism by phase shifting the signal (ES) controlling the sampling of the digital input signal.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: December 21, 1993
    Assignee: Alcatel N.V.
    Inventors: Patrick Ampe, Daniel F. J. Van de Pol, Leon Cloetens