Patents by Inventor Patrick Anthony Coico

Patrick Anthony Coico has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Stress resistant land grid array (LGA) module and method of forming the same
    Patent number: 6964885
    Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.
    Type: Grant
    Filed: January 6, 2004
    Date of Patent: November 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Patrick Anthony Coico, James H. Covell, Benjamin V. Fasano, Lewis S. Goldman, Ronald L. Hering, Sundar Kamath, Kenneth Charles Marston, Frank Louis Pompeo, Karl J. Puttlitz, Jeffrey Allen Zitz
  • Stress resistant land grid array (LGA) module and method of forming the same
    Publication number: 20040141296
    Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.
    Type: Application
    Filed: January 6, 2004
    Publication date: July 22, 2004
    Inventors: Patrick Anthony Coico, James H. Covell, Benjamin V. Fasano, Lewis S. Goldmann, Ronald L. Hering, Sundar M. Kamath, Kenneth Charles Marston, Frank Louis Pompeo, Karl J. Puttlitz, Jeffrey Allen Zitz
  • Stress resistant land grid array (LGA) module and method of forming the same
    Patent number: 6703560
    Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Patrick Anthony Coico, James H. Covell, Benjamin V. Fasano, Lewis S. Goldman, Ronald L. Hering, Sundar M. Kamath, Kenneth Charles Marston, Frank Louis Pompeo, Karl J. Puttlitz, Jeffrey Allen Zitz
  • Stress resistant land grid array (LGA) module and method of forming the same
    Publication number: 20020050398
    Abstract: An integrated circuit module, a land grid array module, and a method for forming the module, include a substrate, which mounts one or more chips or discrete electronic components, and a cap for covering the substrate, and including at least one protrusion coupled to the cap for limiting the amount of flexing of the substrate during actuation. The at least one protrusion can be either rigidly fixed to the cap or adjustably inserted through the cap.
    Type: Application
    Filed: April 19, 2001
    Publication date: May 2, 2002
    Inventors: Patrick Anthony Coico, James H. Covell, Benjamin V. Fasano, Lewis S. Goldmann, Ronald L. Hering, Sundar M. Kamath, Kenneth Charles Marston, Frank Louis Pompeo, Karl J. Puttlitz, Jeffrey Allen Zitz
  • Semiconductor package with low strain seal
    Patent number: 5977625
    Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: David Linn Edwards, Raed A. Sherif, Hilton T. Toy, Shaji Farooq, Patrick Anthony Coico
  • Semiconductor package with low strain seal
    Patent number: 5723905
    Abstract: A semi-conductor packaging structure and a method to reduce the seal strain of the package are disclosed. The structure comprises a cap, substrate, seal and the cap and substrate have a predetermined TCE mismatch. The TCE mismatch between the cap and substrate is predetermined to minimize the seal strain during power-on and power-off use conditions. Preferably, the device has a substrate comprises a ceramic material, a cap with a thermal conductivity of at least about 100 W/m-K. A method of selecting a cap material is disclosed.
    Type: Grant
    Filed: August 4, 1995
    Date of Patent: March 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: Patrick Anthony Coico, David Linn Edwards, Shaji Farooq, Raed A. Sherif, Hilton T. Toy