Abstract: A method for analyzing frequency resources within a predetermined multiplexing band. For at least one base station, capabilities for detecting uplink messages respectively in different frequency sub-bands within the multiplexing band are estimated. For each frequency sub-band, a predetermined service quality criterion is assessed depending on the detection capability estimated for the frequency sub-band. A spectral map of service quality for the base station is transmitted. The spectral map is representative of the frequency sub-bands for which the service quality criterion has been verified and the frequency sub-bands for which the service quality criterion has not been verified.

Abstract: A method for analyzing frequency resources within a predetermined multiplexing band. For at least one base station, capabilities for detecting uplink messages respectively in different frequency sub-bands within the multiplexing band are estimated. For each frequency sub-band, a predetermined service quality criterion is assessed depending on the detection capability estimated for the frequency sub-band. A spectral map of service quality for the base station is transmitted. The spectral map is representative of the frequency sub-bands for which the service quality criterion has been verified and the frequency sub-bands for which the service quality criterion has not been verified.

Abstract: The arrangement includes two basic shift registers (1, 3) which are arranged as multipliers whose initial content is predetermined by an internal key, and which are fed back to each other via a modifying member inserted in the loop. The modifying member (5) is an AND-gate controlled by a signal obtained from an OR-gate (8) to whose two inputs the bits which each come from two shift registers (33, 34) which are independent of the two first registers, are applied. These independent registers are modified one by the other, and this modification is effected by inserted bistable counters (10, 11). In addition, the two basic registers (1, 3) are linearly modified by insertion of bits originating from a source (28, 33, 34) which is external to the register to be modified. Each modifier bit is obtained more specifically from an AND-gate (21-25) to whose inputs the bits coming from the two above-mentioned independent registers (33, 34) are conveyed.