Patents by Inventor Patrick Bohan

Patrick Bohan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250097306
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QOS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Application
    Filed: September 24, 2024
    Publication date: March 20, 2025
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G. Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Patent number: 12132790
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Publication number: 20230022620
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 26, 2023
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G. Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Patent number: 11412052
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Publication number: 20190158606
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: FRANCESC GUIM BERNAT, PATRICK BOHAN, KSHITIJ ARUN DOSHI, BRINDA GANESH, ANDREW J. HERDRICH, MONICA KENGUVA, KARTHIK KUMAR, PATRICK G. KUTCH, FELIPE PASTOR BENEYTO, RASHMIN PATEL, SURAJ PRABHAKARAN, NED M. SMITH, PETAR TORRE, ALEXANDER VUL
  • Patent number: 8793254
    Abstract: In some embodiments, a non-transitory processor-readable medium includes code to cause a processor to send a signal representing a first question and a set of pictogram answers associated with the first question and a second question, different from the first question, and a set of pictogram answers associated with the second question. The first question and the second question can define a health-related survey such as a health-risk assessment. The non-transitory processor-readable medium includes code to receive a user selection of a pictogram answer associated with the first question and receive a user selection of a pictogram answer associated with the second question. The non-transitory processor-readable medium includes code to define a health-related user profile based on the user selection to the first question and the second question.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: July 29, 2014
    Inventors: Nicholas H. Evancich, Patrick Bohan, Grant Verstandig
  • Publication number: 20130212109
    Abstract: In some embodiments, a non-transitory processor-readable medium includes code to cause a processor to send a signal representing a first question and a set of pictogram answers associated with the first question and a second question, different from the first question, and a set of pictogram answers associated with the second question. The first question and the second question can define a health-related survey such as a health-risk assessment. The non-transitory processor-readable medium includes code to receive a user selection of a pictogram answer associated with the first question and receive a user selection of a pictogram answer associated with the second question. The non-transitory processor-readable medium includes code to define a health-related user profile based on the user selection to the first question and the second question.
    Type: Application
    Filed: August 16, 2012
    Publication date: August 15, 2013
    Applicant: Audax Health Solutions, Inc.
    Inventors: Nicholas H. EVANCICH, Patrick BOHAN, Grant VERSTANDIG
  • Patent number: 7096141
    Abstract: In a method and system for testing a device, a tester is operable to generate a first set of test signals for testing the device. The tester is electrically coupled to a test head, which in turn provides electrical coupling to the device. A test assembly is operable to generate a second set of test signals for testing the device. The test assembly is electrically coupled to an interface apparatus, which is adapted to be removably secured to the test head. The interface apparatus is operable to communicate the first and second set of test signals to the device.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: August 22, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Patrick Bohan
  • Publication number: 20050071829
    Abstract: The present invention is directed to a diagnostic compiler for use with a pipeline analog-to-digital converter (ADC) having code sequences corresponding to stages thereof. In one embodiment, the diagnostic compiler includes a transition locator configured to determine transition locations for the code sequences. The diagnostic compiler also includes a characteristics indicator coupled to the transition locator and configured to provide at least one characteristic of the ADC based on the transition locations.
    Type: Application
    Filed: September 26, 2003
    Publication date: March 31, 2005
    Applicant: Texas Instruments Incorporated
    Inventor: Patrick Bohan
  • Publication number: 20050060612
    Abstract: In a method and system for testing a device, a tester is operable to generate a first set of test signals for testing the device. The tester is electrically coupled to a test head, which in turn provides electrical coupling to the device. A test assembly is operable to generate a second set of test signals for testing the device. The test assembly is electrically coupled to an interface apparatus, which is adapted to be removably secured to the test head. The interface apparatus is operable to communicate the first and second set of test signals to the device.
    Type: Application
    Filed: October 14, 2004
    Publication date: March 17, 2005
    Applicant: Texas Instruments Incorporated
    Inventor: Patrick Bohan
  • Publication number: 20050044445
    Abstract: A system for testing a device includes a processor that operates to execute instructions, where the instructions are used to test a device. The processor also operates to generate test signals associated with the test instructions. An interface apparatus is coupled to the processor and operates to communicate the test signals to the device. The interface apparatus includes connectors, where each connector operates to communicate at least one of the test signals.
    Type: Application
    Filed: August 18, 2003
    Publication date: February 24, 2005
    Inventors: William Boose, Dale Heaton, Patrick Bohan