Abstract: Some embodiments of the invention provide novel methods for storing data in a hash-addressed memory and retrieving stored data from the hash-addressed memory. In some embodiments, the method receives a search key and a data tuple. The method then uses a first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. The method also uses a second hash function to generate a second hash value, and then stores this second hash value along with the data tuple in the memory at the address specified by the first hash value. To retrieve data from the hash-addressed memory, the method of some embodiments receives a search key. The method then uses the first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. At the identified address, the hash-addressed memory stores a second hash value and a data tuple.

Abstract: Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix.

Abstract: A buffer arrangement in wire lines in which at least one aggressor wire line is located adjacent and substantially parallel to a victim wire line has a plurality of alternately arranged inverting and noninverting buffers. The alternately arranged in a checkerboard pattern in which noninverting and inverting buffers are located in the victim wire line in locations corresponding to locations of the inverting and noninverting buffers in the at least one aggressor wire line.

Abstract: An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device (418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420).

Abstract: An integrated circuit includes a decision feedback equalizer (DFE) including a first and second digital equalizer logic including circuitry to compensate first and second bits in a received stream and to provide first and second sign bits. The second equalizer logic can run concurrently and can be connected in parallel relative to the first equalizer logic. The second equalizer logic can include a low and high sign bit pipelines providing first and second conditional sign bits by assuming a low and high sign bits, respectively, for a first bits being concurrently processed by the first equalizer logic and a sign bit selection element to select between the first and second conditional sign bits based on the sign bit outcome of the first equalizer logic. The first and second pipelines compensate bits using compensation weights chosen using most recent first and second conditional sign bits and sign bit outcome.

Abstract: An integrated circuit includes at least one latch circuit (300). The latch circuit (300) includes a first stage comprising a latch node (311) positioned between a first pull up device (303) operable to receive a first data signal and a first pull down device (302) operative to receive second data signal. A second stage includes a second pull up device (323) and a second pull down device (322) having the latch node (311) therebetween, wherein at least one gate of the first pull up or first pull down device (302, 303) is directly coupled to a gate of the second pull up or second pull down device (322, 323). An output inverter (330) is coupled to the latch node (311).

Abstract: An integrated circuit (500) includes an array of standard cells including at least a first and a second standard cell (501-504). At least one device in the first standard cell is directly coupled to at least one device in the second standard cell by a gate electrode layer (515) of the integrated circuit. The array of standard cells can implement flip-flops which significantly decrease the switching capacitance.

Abstract: An integrated circuit (200) includes a pulsed buffer (226) having dynamic logic. The dynamic logic includes a first input device (215) coupled to receive a data input signal, a first dynamic node (222), and a first pull up device (224) which when conducting couples the first dynamic node (222) to a positive voltage supply. A first (234) and a second pull down device (238) are connected between the dynamic node (222) and a negative supply operable to discharge the dynamic node (222) when the first input device (215) and both the first and second pull down devices (238, 234) are on. The first pull down device (234) is connected to a first clock signal (CLK), and the second pull down device (238) is coupled to an inverted second clock signal having an odd number of signal inversions being >3 inversions, such as 3 inversions (CLKXXX), relative to the first clock signal (CLK).

Abstract: An integrated circuit (400) includes at least one clocked latch circuit (410). The clocked latch circuit (400) includes a first stage (415) including a latch node (420) positioned between a first pull up device (416) and a first (417) and at least a second pull down device (418), wherein the first stage (415) is operative to receive inputs comprising a data signal (D), a clock signal (CLK) and a clocked complement of the data signal (CDXX). A second stage (441) includes a second pull up device (442) and a third pull down device (445) having the latch node (420) therebetween, wherein at least one gate of the first pull up device (416) and the first (417) and second pull down device(418) is directly coupled to a gate of the second pull up device (442) or the third pull down device (445). An output inverter is coupled to the latch node (420).

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters (62) are arranged in different repeater structures such that the repeater arrangement can be connected to inputs at different locations as a function of the corresponding input as it is physically positioned around the periphery of the crossbar. A pseudo code is provided allowing the repeater structures to be custom configured to corresponding inputs as a function of the desired crossbar as it is designed to be utilized in a particular large integrated circuit, such as a VLSI chip.

Abstract: A circular priority selector, which comprises an input interface (30) for receiving a first N-bit input (REQ<N?1:0>) and a second N-bit input (START<N?1:0>). The selector also comprises a binary tree (34) for searching in the first N-bit input to identify a location of a most significantly asserted value in the first N-bit input, wherein the searching commences at a location responsive to an asserted bit in the second N-bit. The selector also comprises circuitry (320 through 32N-1), responsive to the binary tree, for outputting an output signal indicating a location of the most significantly asserted value in the first N-bit input.

Abstract: A crossbar circuit (30, 40, 50, 60, 70, 80, 90, 100) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters (62) are arranged in different repeater structures such that the repeater arrangement can be connected to inputs at different locations as a function of the corresponding input as it is physically positioned around the periphery of the crossbar. A pseudo code is provided allowing the repeater structures to be custom configured to corresponding inputs as a function of the desired crossbar as it is designed to be utilized in a particular large integrated circuit, such as a VLSI chip.

Abstract: An error-correcting dynamic memory (100) which performs error correction (110) only during refresh or during the second (or subsequent) read of a burst read or during a writeback. Further, the memory may contain an error-correction-code-obsolete bit in addition to data bits and check bits in order to generate check bits during refresh and not during write. This provides error correction without read access delay or write delay at the cost of slightly more exposure to soft errors.

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212).

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and a predetermined plurality of the column locations. Elongate gate conductors (584-602) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). Selected ones (e.g. 514, 544) of the transistors are merged in a row direction if the logic does not require them to be isolated from one another. A plurality of elongate second conductors (222) interconnect to selected ones of the sources or drains of the transistors (224). Non-Boolean portions of the logic circuitry are formed in an adjacent tile section (214) in the semiconductor layer separate from the logic array (212).

Abstract: Random logic circuitry (210) is laid out in a logic array (212) that has a plurality of row and column locations. The logic circuitry (210) implements a plurality of dynamic logic circuits, each logic circuit having a plurality of logic gate field effect transistors (224) each formed at a selected intersection of one of the row locations and one of the column locations. Elongate gate conductors (e.g., G, H, I) are formed at selected row locations in the logic array (212), each gate conductor provided as a gate for one or more of the logic gate transistors (224). A plurality of elongate second conductors (222) connect to selected ones of the sources or drains of the transistors (224) and to non-Boolean portions of the dynamic logic circuits. The non-Boolean portions are formed in an adjacent tile section (214) in the semi-conductor layer separate from the logic array (212).