Patents by Inventor Patrick Buckland
Patrick Buckland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10417167Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: GrantFiled: November 25, 2017Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Patent number: 10417166Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: GrantFiled: November 25, 2017Date of Patent: September 17, 2019Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Publication number: 20180074992Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: ApplicationFiled: November 25, 2017Publication date: March 15, 2018Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Publication number: 20180074993Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: ApplicationFiled: November 25, 2017Publication date: March 15, 2018Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Patent number: 9870335Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: GrantFiled: April 3, 2014Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Patent number: 9870336Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: GrantFiled: February 20, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Patent number: 9705591Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.Type: GrantFiled: June 4, 2015Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Daniel M. Dreps, Nanju Na, Suzanne M. Nolen
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Patent number: 9548808Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.Type: GrantFiled: November 11, 2014Date of Patent: January 17, 2017Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Daniel M. Dreps, Nanju Na, Suzanne M. Nolen
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Publication number: 20160134362Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.Type: ApplicationFiled: November 11, 2014Publication date: May 12, 2016Inventors: Patrick A. Buckland, Daniel M. Dreps, Nanju Na, Suzanne M. Nolen
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Publication number: 20160134363Abstract: Mechanisms, in a data processing system comprising an input/output subsystem implementing an industry standard optical bus, for handling a failure of an optical channel in an optical bus are provided. The mechanisms detect, by failure detection logic of the input/output (I/O) subsystem, failure of an optical channel of the optical bus. The mechanisms send, by a controller of the I/O subsystem, a control signal to channel routing logic of the I/O subsystem to control a routing of data signals between active bus lanes of the data processing system and optical channels of the optical bus in response to detecting the failure of the optical channel. The mechanisms control, by the channel routing logic, routing of data signals between the active bus lanes and the optical channels so as to remove the failed optical channel from further use and use a spare optical channel instead of the failed optical channel.Type: ApplicationFiled: June 4, 2015Publication date: May 12, 2016Inventors: Patrick A. Buckland, Daniel M. Dreps, Nanju Na, Suzanne M. Nolen
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Publication number: 20150286602Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: ApplicationFiled: February 20, 2015Publication date: October 8, 2015Inventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Publication number: 20150286601Abstract: A method, system and computer program product are provided for implementing sideband control structure for Peripheral Component Interconnect Express (PCIE) add-in cards, or cable cards, that utilize cables to connect to input/output (IO) expansion enclosures in a computer system. System firmware uniquely identifies a cable card present in a PCIE slot in a system unit. Enclosure management functions utilize sideband control paths integrated within at least cable providing sideband control signaling, and providing PCIE signaling lanes between the cable card and the IO enclosure.Type: ApplicationFiled: April 3, 2014Publication date: October 8, 2015Applicant: International Business Machines CorporationInventors: Patrick A. Buckland, Jeffery D. Haumont, Gregory M. Nordstrom, William A. Thompson
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Patent number: 8799702Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.Type: GrantFiled: November 19, 2012Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jay R. Herring, Gregory M. Nordstrom, William A. Thompson
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Patent number: 8677176Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device. In response to detecting the failure in the first link, at an IO device end, the first set of lanes is switched with the second set of lanes for exchanging the second set of bussed bits between the first PCIE bridge and the first IO device over the second link using the second set of lanes.Type: GrantFiled: December 3, 2010Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jay R. Herring, Gregory M. Nordstrom, William A. Thompson
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Patent number: 8645747Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.Type: GrantFiled: November 19, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jay R. Herring, Gregory M. Nordstrom, William A. Thompson
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Patent number: 8645746Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.Type: GrantFiled: December 3, 2010Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Patrick A. Buckland, Jay R. Herring, Gregory M. Nordstrom, William A. Thompson
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Publication number: 20120144087Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting the failure in the first link, the first set of bussed bits is exchanged between the first PCIE bridge and the first IO device using an unused portion of a second link connecting a second PCIE bridge and a second IO device.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PATRICK A. BUCKLAND, JAY R. HERRING, GREGORY M. NORDSTROM, WILLIAM A. THOMPSON
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Publication number: 20120144230Abstract: Method and apparatus for providing failover operation for a connection between a first PCIE bridge and a first input/output (IO) device are provided. A first set of bussed bits is exchanged between the first PCIE bridge and the first IO device over a first link using a first set of lanes of the first PCIE bridge. In response to detecting a failure in the first link, at a PCIE bridge end, the first set of lanes is swapped with a second set of lanes of the first PCIE bridge for exchanging a second set of bussed bits between the first PCIE bridge and the first IO device over a second link using the second set of lanes, the second link connecting a second PCIE bridge with a second IO device.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PATRICK A. BUCKLAND, JAY R. HERRING, GREGORY M. NORDSTROM, WILLIAM A. THOMPSON
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Patent number: 7941577Abstract: A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.Type: GrantFiled: June 13, 2008Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Richard L. Arndt, Patrick A. Buckland, Harvey G. Kiel, Renato J. Recio, Jaya Srikrishnan
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Patent number: 7681083Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.Type: GrantFiled: April 18, 2008Date of Patent: March 16, 2010Assignee: International Business Machines CorporationInventors: Richard L. Arndt, Patrick A. Buckland, Gregory M. Nordstrom, Steven M. Thurber