Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.

Abstract: Lane configuration of an interface device of an integrated circuit is described. A core is used to tile a portion of an integrated circuit with a first version of the core and a second version of the core. The core is an application specific circuit version of an interface device. The first version and the second version in combination have a sharable interface. Each of the first version and the second version has N lanes. The first version is a primary version and the second version is a secondary version responsive to a shared interface mode. The N lanes of the second version are combined with the N lanes of the first version via the sharable interface for providing 2-by-N lanes of input/output to the first version.

Abstract: A configurable interface for an integrated circuit is described. The integrated circuit includes a first core, where the first core is an application specific circuit version of a Peripheral Component Interconnect Express (“PCIe”) interface device. First configuration memory cells are associated with the first core, and the first configuration memory cells are for configuring the first core. The first configuration memory cells are programmable responsive to a first portion of a configuration bitstream, and the configuration bitstream is capable of including user-logic information for programming programmable logic of the integrated circuit.