Patents by Inventor Patrick C. Wang

Patrick C. Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5886378
    Abstract: A flash E.sup.2 PROM cell includes a single polysilicon layer part of which makes up the floating gate of a transistor of the cell, part of which makes up an electrode of a capacitor coupled to the floating gate, and part of which makes up the gate of a second transistor of the cell.
    Type: Grant
    Filed: January 10, 1994
    Date of Patent: March 23, 1999
    Assignee: Lattice Semiconductor Corporation
    Inventor: Patrick C. Wang
  • Patent number: 5418390
    Abstract: An E.sup.2 PROM cell includes a substrate of one conductivity type having source and drain regions of an opposite conductivity type disposed along a surface thereof, with a channel region between the source and drain. An oxide layer is formed over the channel region and includes a relatively thick portion over the channel region, and first and second relatively thin portion over respective portions of the source and drain. Programming of the cell is achieved by electrons passing from the floating gate of the device through the thin oxide portion over the source, while erasing of the cell is undertaken by electrons passing from the drain through the thin oxide portion there over into the floating gate. The cell contains only a single layer of polysilicon, which forms the floating gate.
    Type: Grant
    Filed: March 19, 1993
    Date of Patent: May 23, 1995
    Assignee: Lattice Semiconductor Corporation
    Inventor: Patrick C. Wang
  • Patent number: 5359573
    Abstract: In embodiments of flash E.sup.2 PROM arrays, an access transistor is included in each cell thereof, in series with the floating transistor of the cell, the access transistor being used to avoid the problem of drain disturbance in cells other than the cell being programmed. The connection of the control gates in certain of these arrays is such that gate disturbance on the floating gate transistors in those cells not being programmed is reduced or eliminated.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: October 25, 1994
    Assignee: Lattice Semiconductor Corporation
    Inventor: Patrick C. Wang