Abstract: Both the read and write heads are trimmed to approximately 100 nm wide, indicated by Wr and Ww, respectively. The etch depth for the MR element, MR Trenches, is 200 nm and the etch depth for the write head, Write Trenches, is 1 &mgr;m. In order to confirm that inactive regions are actually those selected for irradiation, during trimming the center of the trimmed MR element has been offset by approximately 300 nm from the center of the original MR element. This offset is observed in the final result.

Abstract: A method and a device for write precompensating a data pattern for recording the pattern on a magnetic storage medium at high data rates. A first predetermined write-precompensation delay is applied to the second transition of a burst of transitions of the data pattern. A second predetermined write-precompensation delay is applied to the last transition of a burst. A third predetermined write-precompensation delay is applied to the middle transitions, if any, of a burst. When the burst is a dibit, the application of the second and third predetermined write-precompensation delays is omitted and the first predetermined write-precompensation delay is based on the burst being a dibit. When the burst is a tribit, the application of the second predetermined write-precompensation delay is omitted and the first and third predetermined write-precompensation delays are based on the burst being a tribit.

Abstract: An extremely high density memory array in which every intersection between two insulated orthogonal sets of drive lines define a nonvolatile memory device is described. Each device utilizes the area directly under the intersection of sets of lines to selectively store charges therein under control of suitable writing pulses. Reading is accomplished utilizing capacitive coupling through the device. The array comprises insulated metallic word lines orthogonal to doped bit lines defined within the surface of a semiconductor body. The insulation between the word lines and the bit lines has a dual charge state and is capable of storing charges. A unique structure is utilized whereby a highly doped layer is formed at the surface of the semiconductor body and of the same conductivity type as the body. The bit lines are composed of two distinct layers of an opposite conductivity type to that of said body wherein the layer closest to the surface is less highly doped.