Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.

Abstract: To resolve problems associated with the use of an AUDIO type memory with defective cells without concern for groups of defective cells in such memories, the sounds to be recorded are stored at random addresses, or rather pseudo-random addresses, in the memory. It is shown that, by storing the sounds in this way, it is possible, during the reading operation, by following a same pseudo-random sequence, to restore a coherent sound. At the same time, the device is not demanding in regard to the quality of the memories used.