Abstract: A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.

Abstract: A system may include a resource acquisition engine configured to acquire a set of computing resources for execution of an application flow comprising multiple invocations to an EDA application. The system may also include a resource provision engine configured to provide the set of computing resources for execution of a first EDA process of the EDA application launched by a first invocation in the application flow and identify a second invocation subsequent to the first invocation in the application flow, the second invocation to launch a second EDA process of the EDA application. The resource provision engine may be further configured to, without releasing the set of computing resources provided to the first EDA process, proxy the set of computing resources into a proxied set of computing resources and provide the proxied set of computing resources for execution of the second EDA process of the EDA application.

Abstract: A system may include a set of compute engines. The compute engines may be configured to perform electronic design automation (EDA) operations on a hierarchical dataset representative of an integrated circuit (IC) design. The system may also include a dynamic resource balancing engine configured to allocate computing resources to the set of compute engines and reallocate a particular computing resource allocated to a first compute engine based on an operation priority of an EDA operation performed by a second compute engine, an idle indicator for the first compute engine, or a combination of both.

Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities. The system may also include a resource utilization engine configured to identify an EDA operation to be performed for the EDA application, select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit, and assign execution of the EDA operation to the selected compute unit.

Abstract: A computing system may include an electronic design automation (EDA) data constructor engine and an EDA executor engine. The EDA data constructor engine may be configured to perform, using the local resources of the computing system, a data preparation phase of an EDA procedure for a circuit design. The EDA executor engine may be configured to acquire remote resources for an execution phase of the EDA procedure, wherein the remote resources include remote compute resources and remote data resources remote to the computing system; broadcast constructor data constructed from the data preparation phase of the EDA procedure to the acquired remote data resources; and manage performance of the execution phase of the EDA procedure by the acquired remote compute resources and remote data resources.

Abstract: A system may include a pool of heterogeneous compute units configured to execute an electronic design automation (EDA) application for design or verification of a circuit, wherein the pool of heterogeneous compute units includes compute units with differing computing capabilities. The system may also include a resource utilization engine configured to identify an EDA operation to be performed for the EDA application, select a compute unit among the pool of heterogeneous compute units to execute the EDA operation based on a determined computing capability specific to the selected compute unit, and assign execution of the EDA operation to the selected compute unit.

Abstract: A check for determining the appropriateness of physical design data is provided, where the check includes both a physical component and a logical component. Based upon the logical component of the check, portions of the physical design data that correspond to the logical component are identified and selected. After the portions of the physical design data corresponding to the logical component have been selected, this physical design data can be provided to a physical design analysis tool, along with the physical component of the design check. The physical design analysis tool can then use the physical component of the design check to perform an analysis of the selected physical design data.

Abstract: Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.

Abstract: A system may include a resource acquisition engine configured to acquire a set of computing resources for execution of an application flow comprising multiple invocations to an EDA application. The system may also include a resource provision engine configured to provide the set of computing resources for execution of a first EDA process of the EDA application launched by a first invocation in the application flow and identify a second invocation subsequent to the first invocation in the application flow, the second invocation to launch a second EDA process of the EDA application. The resource provision engine may be further configured to, without releasing the set of computing resources provided to the first EDA process, proxy the set of computing resources into a proxied set of computing resources and provide the proxied set of computing resources for execution of the second EDA process of the EDA application.

Abstract: Methods and apparatus for dynamic distributed resource management as can be used in large-scale electronic design automation processes, are disclosed. In some examples of the disclosed technology, a method for dynamic remote resource allocation includes receiving a request for one or more remote resources, identifying one or more resources available to satisfy the request, initiating one or more separate processes for the respective available resources, preparing the respective resources for use as remote resources, by the one or more separate processes running in parallel, and as a given resource of the one or more available resources completes the preparation, allocating the given resource as a remote resource. In some examples, allocated resources are dynamically integrated into the processing of the job. In some examples, as a given resource of the one or more available resources is allocated, tasking the given resource with a portion of the job.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

Abstract: Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to or beyond the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: Techniques for efficiently determining whether an interconnect line has an impedance component value below a maximum specified value. A specified maximum impedance component value is used to limit the number of interconnect lines that are analyzed by a parasitic extraction analysis process. An analysis window is created based upon the characteristics of the interconnect lines and the specified maximum impedance component value. The size of the window corresponds to the minimum length of the interconnect line that would have the specified maximum impedance component value. Once the analysis window has been created, the interconnect lines are examined to determine if any of them reaches to (or beyond) the analysis window, whereby interconnect lines that exceed the specified maximum impedance component value can be identified.