Patents by Inventor Patrick D.M. Siegl

Patrick D.M. Siegl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10877812
    Abstract: A plurality of hardware accelerators are interconnected and include a special processing unit and accelerator memory. At least one host computer is coupled to each of the plurality of hardware accelerators and includes a general processing unit and host memory. The plurality of hardware accelerators exchange data in a ring communication pattern in computing a linear layer of a neural network.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Patrick D.M. Siegl, Fabio Checconi, Daniele Buono, Alessandro Morari
  • Publication number: 20200081744
    Abstract: A plurality of hardware accelerators are interconnected and include a special processing unit and accelerator memory. At least one host computer is coupled to each of the plurality of hardware accelerators and includes a general processing unit and host memory. The plurality of hardware accelerators exchange data in a ring communication pattern in computing a linear layer of a neural network.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Inventors: Patrick D.M. Siegl, Fabio Checconi, Daniele Buono, Alessandro Morari