Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A method and apparatus for power glitch detection in IC's is disclosed. In one embodiment, a method includes a detection circuit in an IC detecting a voltage transient wherein a value of a supply voltage has at least momentarily fallen below a reference voltage value. Responsive thereto, the detection circuit may cause a logic value to be stored in a register indicating that the detection circuit has detected the supply voltage falling below the reference voltage. The IC may include a number of detection circuits coupled to the register, each of which may provide a corresponding indication of detecting the supply voltage falling below the reference voltage. The detection circuits may be placed at different locations, and thus reading the register may yield information indicating the locations where, if any, such voltage transients occurred.

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract: A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.

Abstract: Monitoring aging information for multiple devices. Aging information of the devices may be received. Statistics regarding the multiple devices may be determined based on the aging information. For at least some of the devices, update information may be determined based on the respective aging information. The update information may include modifications to operating parameters of the devices. For example, the devices may operate according to initial parameters that are above sustainable parameters and the update information may lower the operating parameters based on the aging information.

Abstract: A system and method for testing circuits. A generated input voltage waveform for a first phase of a test may use transitions with a voltage swing between expected low and high trigger points for an integrated circuit (IC) with hysteresis. A generated input voltage waveform for a second phase of the test may use transitions with a voltage swing between the expected low trigger point and a high sub-threshold value. The high sub-threshold value may be a tolerable voltage difference below the expected high trigger point. A generated input voltage waveform for a third phase of the test may use transitions with a voltage swing between the expected high trigger point and a low sub-threshold value. The low sub-threshold value may be a tolerable voltage difference above the expected low trigger point. The expected trigger points and sub-threshold values may be found from earlier characterization studies for the IC.

Abstract: Monitoring aging information for multiple devices. Aging information of the devices may be received. Statistics regarding the multiple devices may be determined based on the aging information. For at least some of the devices, update information may be determined based on the respective aging information. The update information may include modifications to operating parameters of the devices. For example, the devices may operate according to initial parameters that are above sustainable parameters and the update information may lower the operating parameters based on the aging information.

Abstract: In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Abstract: In an embodiment, a test method is implemented to test an integrated circuit that includes at least one processor. The method may include programming a memory to which the integrated circuit is coupled during testing with one or more test programs. The integrated circuit may be booted, and the processor may execute the test programs from the memory. In one embodiment, the memory may also store a control program that may manage the execution of the tests. In an embodiment, the control program may also implement a protocol to communicate with the ATE to perform the testing. The protocol may be implemented over a set of general purpose input/output (I/O) pins, for example. Using the protocol and test vectors on the ATE, the tests may be selected and executed, and test results may be reported.

Abstract: A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Abstract: A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.

Abstract: A computer implemented method for statistical modeling and simulation of the impact of global variation and local mismatch on the performance of integrated circuits, comprises the steps of: estimating a representation of component mismatch from device performance measurements in a form suitable for circuit simulation; reducing the complexity of statistical simulation by performing a first level principal component or principal factor decomposition of global variation, including screening; further reducing the complexity of statistical simulation by performing a second level principal component decomposition including screening for each factor retained in the first level principal component decomposition step to represent local mismatch; and performing statistical simulation with the joint representation of global variation and local mismatch obtained in the second level principal component decomposition step.

Abstract: A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters that can be used to form the device or a respective combination of device characteristics. A model of a figure-of-merit circuit is formed that is representative of an integrated circuit into which the device is to be incorporated. One of the combinations of processing parameters or combinations of device characteristics is identified that results in a device satisfying a set of performance specifications for the figure-of-merit circuit, using the plurality of equations and the device simulator.

Abstract: A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring process factors and a previously defined set of electrical test variables. A set of linearly independent electrical test parameters are formed based on a subset of the set of electrical test variables. The set of process factors is mapped to the linearly independent electrical test parameters. A plurality of figure-of-merit (FOM) performance models are formed based on the process factors. The FOM models are combined with the mapping to enable modeling of IC performance based on the linearly independent electrical test parameters.