Abstract: A wafer defect detection apparatus and a method of fabricating an IC using the same. Images of a plurality of semiconductor wafers forming a wafer lot are captured at a targeted process step of a fabrication flow and preprocessed, wherein a medoid image is identified as a reference wafer image. In one arrangement, preprocessed wafer images of a semiconductor wafer lot may be analyzed for defects based on an ensemble of image analysis techniques using at least one of the reference wafer image from the wafer lot and a template patch to enhance the predictive power of defect detection.

Abstract: A wafer defect detection apparatus and a method of fabricating an IC using the same. Images of a plurality of semiconductor wafers forming a wafer lot are captured at a targeted process step of a fabrication flow and preprocessed, wherein a medoid image is identified as a reference wafer image. In one arrangement, preprocessed wafer images of a semiconductor wafer lot may be analyzed for defects based on an ensemble of image analysis techniques using at least one of the reference wafer image from the wafer lot and a template patch to enhance the predictive power of defect detection.

Abstract: A method for fabricating an integrated circuit includes providing a partitioned chemical-mechanical planarization (CMP) model having a plurality of model parameters that include (i) device specific model parameters and (ii) at least one common parameter. (i) include a pre-CMP thickness of a film including a first material on an in-process device, a post-CMP target thickness for the film on the in-process device, and device group properties that account for device structure for the in-process device. (ii) includes a polish rate from an unpatterned pilot wafer having a second material thereon. The second material need not be the same as the first material. The polish time is automatically determined using the partitioned CMP model. A CMP process is performed on a patterned product wafer having a plurality of the in-process devices using a recipe including the polish time.

Abstract: A method for fabricating an integrated circuit includes providing a partitioned chemical-mechanical planarization (CMP) model having a plurality of model parameters that include (i) device specific model parameters and (ii) at least one common parameter. (i) include a pre-CMP thickness of a film including a first material on an in-process device, a post-CMP target thickness for the film on the in-process device, and device group properties that account for device structure for the in-process device. (ii) includes a polish rate from an unpatterned pilot wafer having a second material thereon. The second material need not be the same as the first material. The polish time is automatically determined using the partitioned CMP model. A CMP process is performed on a patterned product wafer having a plurality of the in-process devices using a recipe including the polish time.