Abstract: Disclosed is a computer-based system and method for conducting ad hoc personal identification, or ID, transactions between at least two or more persons by means of a personal identification transaction apparatus attached to at least two communications channels. The personal identification transaction apparatus is intended to assist the interaction between two persons by brokering an identification transaction thus alleviating the exchange of detailed information necessary to confirm an identity, particularly that portion of a person's identity that is related to the purpose of the interaction between two persons. A component of the personal identification transaction apparatus includes a identification transaction order generation unit that provides a score associated with each user party to the transaction, as well as the transaction itself.

Abstract: A chip multiprocessor (CMP) includes a plurality of processors disposed on a peripheral region of a chip. Each processor has (a) a dual datapath for executing instructions, (b) a compiler controlled register file (RF), coupled to the dual datapath, for loading/storing operands of an instruction, and (c) a compiler controlled local memory (LM), a portion of the LM disposed to a left of the dual datapath and another portion of the LM disposed to a right of the dual datapath, for loading/storing operands of an instruction. The CMP also has a shared main memory disposed at a central region of the chip, a crossbar system for coupling the shared main memory to each of the processors, and a first-in-first-out (FIFO) system for transferring operands of an instruction among multiple processors.

Abstract: In a processor system configured to execute instructions, a method finds an entry in at least one table stored in memory. The method includes (a) storing a first table of multiple entries, each entry including a bit field; (b) storing (i) a first entry of the first table and (ii) a bit size of each entry; (c) storing a sequence of data bits; (d) selecting a portion of the sequence of data bits to produce a data field having a bit size same as the bit size of each entry in the first table; and (e) adding the first entry of the first table to the produced data field to find the entry in the first table.

Abstract: A processing system includes left and right data path processors configured to execute instructions issued from an instruction cache. A vector instruction includes a first word configured for execution by the left data path processor and a second word configured for execution by the right data path processor. The first and second words are issued in the same clock cycle from the instruction cache, and are interlocked to jointly specify a single vector instruction. The first and second words include code for vector operation and code for vector control. The first and second words are concurrently executed to complete the vector operation, free-of any other instructions issued from the instruction cache.

Abstract: A processing system includes left and right data path processors configured to concurrently receive parallel instructions. Left and right accumulators which are, respectively, disposed in the left and right data path processors, are configured to execute an accumulate instruction and obtain an accumulation value. Left and right local memories (LMs) are coupled to the left and right accumulators and configured to store the accumulation value. The accumulation value is equally divided for storage in the left LM and the right LM.

Abstract: A data processing system includes left and right data path processors coupled to an instruction cache. The left and right data path processors, respectively, are configured to execute left and right instruction words received in a single clock cycle from the instruction cache. The left and right data path processors are also configured to operate in a scalar mode and a vector mode. The processors (a) execute the left and right instruction words as two separate instructions in the scalar mode, and (b) execute the left and right instruction words as one instruction in the vector mode.

Abstract: A multiprocessor system for concurrently executing multiple tasks includes first and second processors, each configured to execute at least one task and a local memory physically disposed externally of, and concurrently accessible by the first and second processors. An operating system assigns: (a) a first task to the first processor and a second task to the second processor, the first and second tasks having respective execution resource requirements, (b) a first portion of the local memory to the first processor, and (c) a second portion of the local memory to the second processor. The operating system is configured to initially adjust the first and second portions of the local memory based on the respective execution resource requirements. Portions of the local memory assigned to be shared by the first and second processors may be cooperatively accessed by each of the processors without intervention by the operating system.

Abstract: An image processing system encodes a natural image into a segmented or mosaic image having well-defined edges and a residual image. The segmented image is encoded using a lossless encoding technique while the residual image is encoded using a lossy technique. This encoded image may be recorded on a video tape such that the segmented image may be recovered in picture-in-shuttle modes such as fast forward and fast rewind. In addition, the recorded image may be decoded and reencoded through several generational levels without experiencing significant degradation in perceived image quality. The segmented image is produced by an encoder which employs a multi-scale edge finder that is able to resolve transitions occurring over two, four and eight pixels into an edge located between two pixels.

Abstract: An edge finder for an image processing system locates edges in a digitized image over several different ranges of pixel values and assigns, to each pixel value an edge characteristic value which represents a minimum edge value for the pixel in the image. The exemplary edge finder that is able to resolve transitions occurring between two pixels or over groups of four or eight pixels to determine whether an edge should be defined between the original two pixels. The edge finder simultaneously examines four edges in two dimensions to determine the edgeness value for each pixel in the digitized image.