Abstract: According to certain aspects, a system includes frequency measurement devices distributed across a power domain on a chip, wherein the power domain is divided into multiple power sub-domains, and each of the power sub-domains includes a respective subset of the frequency measurement devices. The system also includes a power manager. For each of the power sub-domains, the power manager is configured to receive frequency measurements from the respective subset of the frequency measurement devices, and determine a supply voltage setting for the power sub-domain based on the received frequency measurements from the respective subset of the frequency measurement devices.

Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.

Abstract: Metal thermal grounds are used for dissipating heat from integrated-circuit resistors. The resistors may be formed using a front end of line layer, for example, a titanium-nitride layer. A metal region (e.g., in a first metal layer) is located over the resistors to form a heat sink. An area of thermal posts connected to the metal region is also located over the resistor. The metal region can be connected to the substrate of the integrated circuit to provide a low impedance thermal path out of the integrated circuit.

Abstract: A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

Abstract: The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.