Abstract: A set of a plurality of bits is processed by performing operations on the set of bits to produce a result that identifies whether the set of bits has a bit pattern and that identifies a location of the bit pattern in the set of bits. For a set of bits for an outgoing bitstream, one or more bits are inserted in the set of bits relative to the bit pattern if the set of bits has the bit pattern. For a set of bits for an incoming bitstream, one or more bits in the set of bits relative to the identified bit pattern are removed if the set of bits has the bit pattern and if the identified bit pattern comprises data bits.

Abstract: A system adds functionality to a power button where use of the power button controls the entry and exit from a diagnostic mode. The system includes an information appliance connected to a diagnostic appliance. Once an information appliance is powered up, the information appliance monitors its power button for a press which indicates a request to enter a diagnostic mode. Absent a press of the power button, the system continues to be under control of the information appliance and never enters a diagnostic mode. However, if a press of the power button is detected, the system enters a diagnostic mode. Once in a diagnostic mode the system provides an exit therefrom by interpreting a power button press as a request to exit. The window of time to make such an exit closes once the diagnostic appliance achieves communication with the information appliance. If the power button is pressed during this window of time, then the system ends its diagnostic mode and control of the system returns to the information appliance.

Abstract: A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.

Abstract: A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.

Abstract: A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other (non-interrupt) tasks. The interrupt sources may record interrupt service requests instead of signalling an interrupt to the processor. Periodically, the processor may poll the interrupt sources to determine if a service request is recorded.

Abstract: A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer.

Abstract: An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data.