Abstract: An interface circuit having a first reference terminal and a first input terminal for receiving a first input current signal, referenced to said first reference terminal from a first input current signal source. The circuit also has a second reference terminal and a second input terminal for receiving a second input current signal referenced to said second reference terminal from a second input current signal source. The second input current signal has a first and second signal current level. The interface circuit comprises a first receiver means coupled between the first input terminal and a first receiver means reference terminal. The first receiver means is responsive to the first input current signal first and second signal current levels for providing a first output signal at respective first and second levels. The first output signal is referenced to the second reference potential at a first signal output terminal.

Abstract: A universal solid state power controller for controlling the application of a source voltage to a load comprising a semiconductor switch having a predetermined non-bounce switching characteristic. The switch is responsive to an operating signal for connecting the load to the source voltage. A control means has a microcomputer following a predetermined program. The control means is responsive to a command electrical signal and provides the semiconductor switching means operating signal. The microcomputer program has an ac subprogram for SSPC operation with a source voltage of sinusoidal character and a dc subprogram for SSPC operation with a source voltage of direct current character. A voltage selection circuit provides a logic signal of a first polarity to the microcomputer to direct the microcomputer to use the ac subprogram for SSPC operation with an ac source. The logic signal has a second polarity to direct the microcomputer to use the SSPC dc subprogram for operation with a dc source.

Abstract: A solid state dc switch for switching power from the positive terminal of a ground referenced dc voltage source to the terminal of a ground referenced load. The solid state switch has a divide-by-two circuit means responsive to a clock signal and to a control signal first state for providing first and second symmetrical output signals at a frequency of one-half the frequency of said clock frequency. It also has a transformer drive and rectifier means for providing an isolated dc signal. An isolated switching means is included which is responsive to the high state of an isolated dc signal, having a transistor switch having a collector, an emitter and a base, the collector being coupled to a positive terminal of a ground referenced voltage source. The emitter is coupled to the return of the ground referenced load. The base is coupled to an isolated dc signal.

Abstract: A solid state power controller off-line capacitor divider power supply coupler between an ac voltage source output terminal and neutral terminal, supplying regulated dc voltage levels referenced to the ac voltage source output terminal to a load such as the control and drive circuits of a solid state power controller. The invention circuit comprises an input capacitor having a first and second terminal. The capacitor first terminal is coupled to the ac voltage source neutral terminal. A first diode has an anode and a cathode; the anode is coupled to the capacitor second terminal. A positive filter capacitor has a first and second terminal. The first terminal being coupled to the first diode cathode and the filter capacitor second terminal being coupled to the control and drive circuit reference terminal. The invention circuit has a first positive regulator means with an input terminal, an output terminal and a reference terminal. The input terminal is coupled to the filter capacitor first terminal.

Abstract: An isolated low power thyristor gate drive circuit for driving the gate of a thyristor having an anode and a cathode. The drive circuit is responsive to a signal voltage from a signal source. The signal voltage is sourced with respect to a first reference potential to the low power gate drive circuit. The invention circuit has a dual polarity source (DPS) responsive to the signal source for providing a positive drive signal having a positive polarity with respect to a second reference potential and a negative drive signal having a negative polarity with respect to the second reference potential. A normally open semiconductor device network has a current sink terminal, a current source terminal, and a gate terminal. A normally conducting semiconductor device has a current sink terminal, a current source, and a control terminal.The normally open semiconductor device network current sink terminal is coupled to the thyristor anode.

Abstract: An electrical switch or power controller is provided controlling the application of a source voltage to a load under the control of an electrical command signal, resulting in the development of a load current in response to said electrical command signal comprising: a semiconductor switching means having a predetermined non-bounce switching characteristic, being responsive to a semiconductor switching means operating signal for connecting said load to said voltage, an electromechanical switch means having a low voltage drop in a conducting condition, being responsive to an electromechanical switching means operating signal and being connected in parallel with the semiconductor switching means for connecting the load to the source voltage, control means responsive to the command electrical signal for providing the semiconductor switching means operating signal and the electromechanical switching means operating signal, whereby the semiconductor switching means predetermined non-bounce switching characteristics

Abstract: A monolithic solid state power controller generally comprises a power supply, zero voltage crossing detector, operator interface circuitry, current sensing and trip timing logic (having zero current detection capability), drive circuitry, and a power switch. The current sensing and trip timing logic functions are implemented in a monolithic device which provides flexible mode of operation of the switch, operator command validation, status and mode indication, drive enablement in synchronization with zero voltage crossing of the source voltage, and tripout operation in synchronization with zero current crossing in the load current. Both fast trip (in response to catastrophic overcurrent) and timed trip (in response to overcurrent conditions occurring over a period of time) capabilities are provided.