Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Abstract: Disclosed herein is a design structure for route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.

Abstract: Disclosed herein is a method of route planning for global positioning system (GPS) based navigation systems. The method identifies route segments used in a GPS based navigation system and records an actual historical time of travel for at least one route segment traveled by users of the GPS based navigation system travel. The actual historical time of travel comprises the amount of time taken by a user of the GPS based navigation system to go from a beginning of the route segment to an end of the route segment. With embodiments herein, the day and time that the route segment was recorded is also noted. Then, the actual historical time of travel and the day and time for the route segment can be stored in a database. This information can be stored for a single-user or can be combined from a plurality users of the GPS based navigation systems.

Abstract: Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

Abstract: A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

Abstract: A system and method for determining the operational state of a logic device having a plurality of shadow registers, each associated with one of a plurality of functional registers. Data stored in a functional register is, under selected conditions, also stored in an associated shadow register. These conditions include without limitation receipt by the functional register of predetermined event information such as an opcode, memory address or other information. Data in a given set of functional registers, e.g., registers making up pipeline stages in a microprocessor, may be stored in shadow registers simultaneously or sequentially when given data reaches a given register in the set. Additionally, data is stored in the shadow registers without interrupting execution cycles of the logic device.

Abstract: Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

Abstract: A processor with multiple equivalent functional units for power reduction, which includes a mechanism for controlling the selection of functional units. Specifically, the processor comprises a first circuit performing a predetermined function at a first speed, a second circuit for performing the same predetermined function at a second speed, and a control system for selecting either the first or second circuit to perform the function. The control system further includes a mechanism for controlling the rate of execution of the processor instructions in the pipeline in order to compensate for the speed at which the first or second circuit was performing the predetermined function.

Abstract: A logic circuit device and circuit design methodology includes a “split-book” logic circuit design having different active device sizes with outputs for connections to both critical and non-critical digital circuit paths. By using “split” book designs with separate input and output stages, better silicon utilization, power optimization, and performance results. This is because each split book is designed with multiple output buffers that may be configured to optimally drive critical and non-critical paths. During the power/performance optimization phase of the design, timing critical paths of the design are first identified, with each path being optimized on its own basis. First the input stage of the strand may be improved with a stronger drive on the input port of the book. Only the input port that has been linked to a critical path is updated. The other input pins are left at their default setting.

Abstract: A low powering apparatus for automatic reduction of power in active and standby modes is disclosed. The low powering apparatus includes a state detector, a margins of safety device and a positioning device. The state detector detects a first or second state, such as a standby state and an active state, that has predominated in a recent past. The margins of safety device indicates safe low power margins in correlation to the detected first or second state. The positioning device adjusts the power level according to the outputs of the state detector and margins of safety device. Thus, the low powering apparatus minimizes the power level of a system at the first or second state without compromising full performance of the system.

Abstract: Disclosed is a tristate circuit driver capable of both parking the output in a deasserted state and switching to a tristate mode in less than one clock cycle. In a preferred embodiment, the driver circuitry utilized a delay device to generate a pulse signal immediately after the transition in an enable signal is detected. The pulse signal then causes the tristate driver to output a signal of a predetermined voltage for a duration of less then one clock cycle.

Abstract: A wiring layout design method and system providing efficient routing of wiring paths between multiple function blocks in an integrated circuit is disclosed. Associated with the function blocks are logic service terminals (LSTs) aligned on-grid relative to the global wiring layout. The technique utilizes a locator designating a desired contact point for each on-grid LST to be connected. The contact point designation is made without restriction relative to the predetermined grid pattern of the logic service terminals. Subsequent use of a conventional global wiring layout program to generate a layout of connections between LSTs, a reformatting program connects each wired logic service terminal to its desired contact point on the associated function block using the corresponding locator.

Abstract: A current limiting clamp circuit for providing a clamped voltage at a node and including a P-type MOS transistor and several N-type MOS transistors which are connected in series between the drain of the P-type MOS transistor and ground, with one of the N-type transistors having its gate and drain connected to the drain of the P-type transistor, and having its source connected to the node. In another embodiment, the current limiting clamp circuit includes a pair of P-type transistors and several N-type transistors, with one of the P-type transistors having its source connected to a power supply, its gate connected to ground and its drain connected to the source of the other P-type transistor which has its gate and drain connected to the node.