Abstract: In order to provide communication between two processors in a data processing system, a target processor includes apparatus that can store data signal groups from a source processor. Having stored a data signal group from the source processor, the target processor notifies the source processor of the receipt of the data signal group. In response to the presence of the stored data signal group, the target processor executes a interprocessor command or instruction identified by the transferred data signal group. The source processor at a preselected time, executes an instruction to determine if the command designated by the data signal group stored in the target processor has been executed. The commands specified by the transferred data signal groups can be executed under hardware control by the target processor in a relatively short time immediately following completion of the instruction in execution in the target processor at the time of the transfer of the data signal group.

Abstract: In a data processing system, a measurement of the cumulative time used in the performance of an intermittent activity can be required. To determine this cumulative time, a memory location is designated during initialization that is to contain the value of the system clock determined at each initiation of the intermittent activity. A second memory location is provided during initialization that is to contain the accumulated total of the measurements taken to perform the intermittent activity. At each termination of the intermittent activity, the contents of the first and second locations are retrieved from the main memory. The value stored in the first main memory location is then subtracted from the system clock value at the termination of the current intermittent activity and the resulting value is added to the contents of the second location. The resulting value of the addition operation is then stored in the second main memory location.

Abstract: In combination with a multiprocessing and multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new architecture for the execution of the call instruction, the return instruction, and the trap procedure is implemented partly in firmware and partly in hardware. The architecture includes a new stack mechanism for storing hardware managed control information in a control frame and software controlled data in a data frame.

Abstract: In a computer system having a plurality of processors and processes, a semaphore architecture for communication with and between the processes in order to effects coordination and cooperation between processes. The invention is implemented in firmware and software, and divides the work of an entire semaphore operation such that the simple part of the P and V operations (which deliver and pick-up signals to and from the processes, respectively) is done by the firmware; whereas the difficult work of the P or V operation is done by software. Thus the improved architecture increases the speed of the system by the use of firmware and increases the flexibility of the computer system by utilizing software to change functionality.

Abstract: In combination with a multiprocessing/multiprogramming computer system having a ring protection mechanism for protecting computer programs from unauthorized access, a new call instruction architecture is implemented partly in firmware and partly in hardware. Also, a new stack mechanism stores hardware managed control information in a control frame and software controlled data in a data frame.