Abstract: The present disclosure describes systems and methods for adjusting a logic network. The method includes adding, to the logic network, a first redundant node and determining a first adjustment to a first node of the logic network within a transitive fanin of the first redundant node. The method also includes making the first adjustment to the first node based on determining that a first gain based on the first adjustment satisfies a threshold.

Abstract: Embodiments herein describe selecting a gate in a mapped network and then un-mapping the gate from a library cell into a Boolean expression. Resubstitution can be performed on the gate to determine whether its logic can be simplified using, e.g., a don’t care set and candidate divisors within a window of the gate. If a new Boolean expression resulting from performing resubstitution has an equivalent function, the gate can be re-mapped using the new Boolean expression, which can reduce the area of a circuit design corresponding to the mapped network. These steps can be performed iteratively on the mapped network.