Abstract: A code word generator for OVSF codes, comprising an intermediate memory device (16) which is used to input a calculation index as a binary calculation index data word, a calculation device (17) which permutes the significant data bits of the calculation index data word bit-by-bit so that a calculation basis (B) can be generated, a counter (21) for producing a counting variable (Z) and provided with a logic circuit comprising several AND gates for bit-by-bit linkage of the counting variables (Z) generated with the calculation basis (B) in order to form a linking data word and several XOR gates for logical reduction of the linking data word to form code word data bits of the OVSF code word.