Abstract: A USB Type-C receiver device, includes: a port including a channel configuration input; a ground pin; and a protection circuit for protection against high voltages on the channel configuration input, wherein the protection circuit includes a resistive circuit coupled between the channel configuration input and the ground terminal and configured to form both a voltage divider and a resistive pull-down circuit coupled between the channel configuration input and the ground pin.

Abstract: A USB Type-C receiver device, includes: a port including a channel configuration input; a ground pin; and a protection circuit for protection against high voltages on the channel configuration input, wherein the protection circuit includes a resistive circuit coupled between the channel configuration input and the ground terminal and configured to form both a voltage divider and a resistive pull-down circuit coupled between the channel configuration input and the ground pin.

Abstract: A method is for controlling a change of an electromechanical component between a first operating state and a second operating state. The method may include changing from the first operating state to the second operating state by generating a first current flowing through the electromechanical component, prior to the generation of the first current, charging a capacitor, and simultaneously with the generation of the first current, partial discharging the capacitor through the electromechanical component to cause an additional current to flow in the electromechanical component, the additional current being added to the first current. The method may include changing from the second operating state to the first operating state by generating a second current flowing in a direction opposite to the first current in the electromechanical component, and prior to the flowing of the second current, discharging the capacitor.

Abstract: A method is for controlling a change of an electromechanical component between a first operating state and a second operating state. The method may include changing from the first operating state to the second operating state by generating a first current flowing through the electromechanical component, prior to the generation of the first current, charging a capacitor, and simultaneously with the generation of the first current, partial discharging the capacitor through the electromechanical component to cause an additional current to flow in the electromechanical component, the additional current being added to the first current. The method may include changing from the second operating state to the first operating state by generating a second current flowing in a direction opposite to the first current in the electromechanical component, and prior to the flowing of the second current, discharging the capacitor.

Abstract: The method of protecting a secret key from being read by a non-secure software application, comprises a step (94) of recording the secret key as a routine stored in an executable-only memory. The routine having: load instructions to load the secret key into a memory readable by a secure and a non-secure software application, if the routine is called by the secure software application, and control instructions to leave only dummy data instead of the secret key in the readable memory if the software application calling the executable-only routine is the non-secure software application.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1, C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1, C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2, C1) by means of a command designating the second address.

Abstract: A semiconductor device having circuitry comprising an embedded memory, an embedded processor for executing application codes, and a functional hardware element coupled with the embedded memory via a protected bus, and with the embedded processor via an unprotected bus, the hardware element being arranged to protect the protected bus, and including a locking means comprising at least one lock bit for globally locking at least part of the locking means before executing the application code.

Abstract: A data processing device (D) comprises an external memory (EM) for storing data defining at least part of a program in an Endian form, and an integrated circuit (IC), connected to the external memory (EM), via a memory bus (MB) having an N-bit width, and comprising i) an embedded processor (EP) adapted to run the program, ii) an internal memory (IM) for storing at least a bootstrap code of this program, iii) an external memory interface (EMI) connected to the memory bus (MB), and iv) a processor bus (PB) connecting the internal memory (IM) and the external memory interface (EMI) to the embedded processor (EP). The external memory (EM) also stores, at a chosen address, an N-bit data word (C) having a value representative of its size (equal to N/8 bits) and of the Endian form of the stored program data.

Abstract: A control device (D) is a part of an integrated circuit (IC) comprising at least two cores (C1,C2) coupled, via buses (BC1, BC2), to a memory (M) arranged to store data to be transferred between these cores (C1, C2). This control device (D) comprises at least one flag register (FR1, FR2) coupled to the cores (C1,C2) via the buses (BC1, BC2) and arranged to store, at Ni addresses, Ni flag values associated to data stored into the memory (M) by one of the cores and ready to be transferred towards the other core, each flag value stored at a first address being able to be set or reset by one of the cores (C1, C2) by means of a command designating the first address, thus authorizing another flag value stored at a second address to be simultaneously set or reset by the other core (C2,C1) by means of a command designating the second address.

Abstract: The method of protecting a secret key from being read by a non-secure software application, comprises a step (94) of recording the secret key as a routine stored in an executable-only memory. The routine having: load instructions to load the secret key into a memory readable by a secure and a non-secure software application, if the routine is called by the secure software application, and control instructions to leave only dummy data instead of the secret key in the readable memory if the software application calling the executable-only routine is the non-secure software application.