Abstract: Aspects of technology disclosed herein relate to techniques of a full-circuit simulation-based circuit design verification. A simulation is performed to determine current data of parasitic resistors in one or more parasitic resistance networks in power supply circuitry of a circuit design by injecting a current into each one of the one or more parasitic resistance networks. Based on the current data, non-current carrying parasitic resistors are removed from the one or more parasitic resistance network to generate one or more reduced parasitic resistance network. Using the one or more reduced parasitic resistance networks, a full-circuit simulation is performed to obtain current density information. A circuit design verification of the circuit design is then performed based on the current density information.

Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Abstract: For one or more geometric elements partitioned into a plurality of geometric element portions, the expected current directions through each geometric element portion are determined. Using the expected current directions, each expected current path through the geometric element portions is determined. Based upon the expected current paths, and the physical characteristics represented by the geometric element portions in those expected current paths, the electromigration features corresponding to the geometric element or elements are determined. For example, the length of the longest expected current path through the geometric element or elements can be identified based upon the lengths of the geometric element portions and the directions of their currents, and this length can then be compared with the Blech length for the geometric element or elements.

Abstract: Aspects of the invention relate to techniques for determining the electromigration features corresponding to layout design data. According to various examples of the invention, a circuit design is analyzed to determine voltages of nodes in an interconnect tree. From the voltages of the nodes, current density values and current directions for the segments of the interconnect tree are determined. Based on the current density values and the current directions, hydrostatic stress values for the nodes are computed under a steady-state condition and conservation of the conductive material within the interconnect tree. The electromigration susceptibility of the interconnect tree is then determined based on the computed hydrostatic stress values.

Abstract: A network device is arranged to transmit a specific identification such as the device's MAC address in Next Pages of auto-negotiation and to determine a link status to be ‘down’ if ‘Next Pages’ containing that address are received by the same port. The invention avoids the use of signal detect pins for fiber optic links.

Abstract: A method of calculating electrical interactions of circuit elements in an integrated circuit layout without flattening the entire database that describes the layout. In one embodiment, a hierarchical database is analyzed and resistance and capacitance calculations made for a repeating pattern of elements are re-used at each instance of the repeated pattern and adjusted for local conditions. In another embodiment, a circuit layout is converted into a number of tiles, wherein the resistance and capacitance calculations made for the circuit elements in the center and a boundary region of the tiles are computed separately and combined. Environmental information that affects electrical interaction between circuit elements in different levels of hierarchy is calculated at a lower level of hierarchy so that such calculations do not need to be made for each placement of a repeated cell and so that not all interacting elements need to be promoted to the same hierarchy level to compute the electrical interactions.

Abstract: A hydraulic fluid storage apparatus for a transmission has a main sump and a secondary sump. The secondary sump is connected with the main sump through a restricted flow passage. The fluid within the main sump is subjected to centrifugal forces by rotating components within the transmission, such that at high speeds and high levels in the main sump, the restricted passage is closed by a centrifugal dam thereby resulting in fluid storage within the secondary sump. The fluid storage in the secondary sump returning to the main sump when the speed of the rotating components is reduced.

Abstract: A detector for determining which interface protocol is in use by a serialiser/deserialiser, and comprising detecting channels composed of clocked delays and bit comparators for detecting the presence of idle signals coded according to either ten-bit or five-bit protocols using either one or two clocks.

Abstract: A FIFO store for data packets and their respective status words includes space for the writing of a predetermined sync word or one of a cyclic sequence of predetermined sync words with each status word. The sync word can be used to prevent forwarding of a packet and as an aid to fault diagnosis if on reading the status word the sync word does not match any of the predetermined sync words.

Abstract: A network device incorporating selective compression of stored data packets is disclosed. The network device receives, stores and forwards data packets and includes a system for applying a compression algorithm to packets after their header portions and storing the partially compressed packets, which are decompressed after readout from storage and before they are forwarded. Lengths of a packet as received and as subject to the compression algorithm are compared to prevent storage when the algorithm fails to produce a shorter packet.

Abstract: A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and structure responsive to data in said the packets for directing received packets to the transmit ports. In respect of at least one of the transmit ports the switch includes an output buffer for storing data packets before they are forwarded from the port and an allocation controller. The allocation controller allocates each packet destined for the buffer and each packet leaving the buffer for the port into at least one of a plurality of categories, which may be based on priority or protocol data and may define traffic types such as video or audio.

Abstract: A network switch includes a plurality of receive ports for receiving addressed data packets and a plurality of transmit ports for forwarding the addressed data packets and is responsive to data in the packets for directing received packets to the transmit ports. The switch includes, with respect to at least one transmit port, a bandwidth controller for at least one selected packet type. The bandwidth controller diminishes an aggregate count in response to the sizes of packets of the one type destined for the transmit port and continually augments the aggregate count at a selectable rate. The switch compares the aggregate count with a threshold and initiates a discard of packets of the one type before they can be forwarded from the transmit port so as to limit the proportion of available bandwidth occupied by packet so of the one type with respect to the transmit port.

Abstract: An application specific integrated circuit includes a multiplicity of operational blocks each of which includes at least one respective data bus and at least one respective visibility bus and a respective addressable multiplexer for selecting between those buses to provide an output on a to respective block bus. An interface block includes a first addressable multiplexer for selecting output data from a selected one of the blocks and providing an output; a register coupled to the output of the first addressable multiplexer; and a second addressable multiplexer for selecting between data provided by the output of the first addressable multiplexer and data in the register. Different portions of externally supplied address words are applied to the first addressable multiplexer and the respective addressable multiplexer, and a decoder is responsive to the address words for controlling the second addressable multiplexer. The arrangement provides a common multiplexing system for data buses and visibility buses.

Abstract: A network switch includes a transmit queue of packets along with indication (e.g. in respective status words) of the type of each packet and its size. An arbitrator includes a counter which is incremented by the size (e.g. in bytes) of each packet of a first type (e.g. ‘low-loss’) and decremented by a scaled size of each packet of a second type (e.g. ‘normal loss’). If the queue exceeds a set limit, preferably less than the maximum possible size of the queue, packets are discarded if a scaled packet of the second type exceeds the net content of the counter.

Abstract: A network device which is arranged to transmit a specific identification such as the device's MAC address in Next Pages of auto-negotiation and to determine a link status to be ‘down’ if ‘Next Pages’ containing that address are received by the same port The invention avoids the use of signal detect pins for fiber optic links

Abstract: A detector for determining which interface protocol is in use by a serialsier/deserialiser and comprising detecting channels composed of clocked delays and bit comparators for detecting the presence of idle signals coded according to either ten-bit or five-bit protocols using either one or two'clocks

Abstract: A network device which includes flow control, being responsive to a control frame prescribing a pause in the forwarding of packet from a port, sorts received packets intended for forwarding from that port into a first queue, e.g. critical latency traffic and at least one other queue. A count of the number of packets in the first queue is determined at the onset of a pause and at least that number of packets are discarded from the first queue if the pause time exceeds a programmable reference.

Abstract: A FIFO store for data packets and their respective status words includes space for the writing of a predetermined sync word or one of a cyclic sequence of predetermined sync words with each status word. The sync word can be used to prevent forwarding of a packet and as an aid to fault diagnosis if on reading the status word the sync word does not match any of the predetermined sync words.