Abstract: A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit.

Abstract: A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit.

Abstract: The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the h

Abstract: The sample-and-hold device comprises a holding capacitor and operates according to a track phase during which the voltage on the terminals of the capacitor tracks the input signal and according to a hold phase during which the capacitor is isolated from the input signal, it comprises: a differential pair comprising a first transistor Q1 and a second transistor Q2 connected as common emitters, the collector of the transistor Q2 being connected to the holding capacitor, the input signal being applied to the base of the transistor Q1; a third transistor Q3, of which the base is connected to the collector of the transistor Q2 and the emitter is connected to the base of the transistor Q2, the signal present on the emitter of the transistor Q3 forming the output signal of the sample-and-hold device; a current source I connected to the collector of the transistor Q2; during the track phase, the differential pair Q1, Q2 being supplied by a current 2I, the transistor Q2 being charged by the current source and by the h

Abstract: A method for generating a digital signal representative of the pairing error between the channels of an analog digital conversion system with time interleaving, and a method for suppressing the errors thus calculated and an analog digital conversion system with time interleaving using same. The method comprises determining a spectrum (11-12) of the digital signal as a function of a frequency response of the analog digital conversion system with time interleaving (CAN 10) to at least one analog calibration signal (IC), and generating a “comb” signal whose spectrum is composed of frequency lines kFs/N, where Fs is a sampling frequency and N a number of channels of the analog digital conversion system with time interleaving, and whose amplitude is dependent on the frequency response of the analog digital converter.

Abstract: The invention relates to a method for generating a digital signal representative of the pairing error between the channels of an analog digital conversion system with time interleaving, a method for suppressing the errors thus calculated and an analog digital conversion system with time interleaving using same. The present invention proposes a less complex digital solution since it does not require the extraction of the defects of the signal at the output of the converter. It makes it possible to correct the pairing errors by the direct creation of digital signals representative of these errors, and their subtraction from the digitized signal at the output of the conversion system. An object of the invention is a method for generating a digital signal representative of the pairing error between the channels of an analog digital conversion system with time interleaving (CAN 10) comprising an analog digital converter (CAN1, CAN2,...,CANN) on each channel.