Patents by Inventor Patrick Guilloteau

Patrick Guilloteau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic block protection system
    Patent number: 8547136
    Abstract: An integrated circuit (IC) with an Intellectual Property (IP) protection system is disclosed. The IC includes a memory array operable to store a key. The key is a sequence of binary bits. The IC also has an IP block operable to perform a function. The IP block is defined through the circuitry of the IC. The IP block is also operable to be activated with the key. The IC has an interconnection operable to couple the memory array to the IP block. The interconnection transfers the key from the memory array to the IP block. A method to configure and to operate the IC is also provided.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: October 1, 2013
    Assignee: Altera Corporation
    Inventor: Patrick Guilloteau
  • Method and system for using boundary scan in a programmable logic device
    Patent number: 7550995
    Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 23, 2009
    Assignee: Altera Corporation
    Inventors: Patrick Guilloteau, Rafael C. Camarota, Arun Kumar Varadarajan Rajagopal
  • Method and system for using boundary scan in a programmable logic device
    Patent number: 7248070
    Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 24, 2007
    Assignee: Altera Corporation
    Inventors: Patrick Guilloteau, Rafael C. Camarota, Arun Kumar Varadarajan Rajagopal