Patents by Inventor Patrick H. Buffet

Patrick H. Buffet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080320424
    Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.
    Type: Application
    Filed: September 4, 2008
    Publication date: December 25, 2008
    Inventors: Timothy W. Budell, Patrick H. Buffet, Craig P. Lussier
  • Patent number: 7454723
    Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Budell, Patrick H. Buffet, Craig P. Lussier
  • Patent number: 7146596
    Abstract: An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Thomas R. Bednar, Timothy W. Budell, Patrick H. Buffet, Alain Caron, James V. Crain, Jr., Douglas W. Kemerer, Donald S. Kent, Esmaeil Rahmati
  • Patent number: 7064570
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Grant
    Filed: September 20, 2003
    Date of Patent: June 20, 2006
    Assignee: International Business Machines, Corporation
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Patent number: 7038319
    Abstract: A semiconductor chip package with reduced cross-talk between adjacent signals in a layer of a carrier is disclosed. A first pair of conductors for carrying a first signal is provided in a layer of the carrier. A second pair of conductors for carrying a second signal is provided adjacent to the first pair of conductors in the layer, where the first and second pairs of conductors are configured such that cross-talk between the first and second pairs of conductors is substantially minimized, without increasing the size of the package. The height of the first pair of conductors is shorter than the second pair of conductors. Alternatively, the first and second pairs of conductors are configured so that they evenly affect each other. The chip package thus reduces the cross-talk without compromising the density of the interconnections in the package or resulting in an increase in the size of the package.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: May 2, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Charles S. Chiu, Jon D. Garlett, Louis L. Hsu, Brian J. Schuh
  • Patent number: 7017128
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Patent number: 7000203
    Abstract: Disclosed is an improved method of determining mutual inductance of wires in an electronic design. First, the invention selects a pair of wires. Then, the invention adds concentric ring lines to the design. The invention then adds straight line segments representing each wire between points where each corresponding wire crosses the adjacent ring lines. Each of the straight lines run from a point where a corresponding wire crosses an outer concentric ring line to a point where the corresponding wire crosses an inner concentric ring line. The invention can then very simply calculate the mutual inductance between the straight line segments (not the actual potentially non-linear wires themselves). The mutual inductance of the straight line segments only comprises an approximate mutual inductance of the wires because the actual mutual inductance of the wires may be slightly different if the wires are non-linear.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Charles S. Chiu, Gustina B. Collins, Craig P. Lussier
  • Patent number: 6978214
    Abstract: An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of second ports on a second side of the substrate, for each electrical network. All of the first ports are electrically isolated from one another. All of the second ports are electrically connected to a common voltage. A computer readable program code, which is executed by a processor of a computer system computes for a first electrical network of the at least one electrical network an electrical resistance between each first port and a port of the second ports. The computer code may also display a perspective plot of the computed electrical resistances as a bar oriented about normal to each first port.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: December 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Budell, Patrick H. Buffet, Craig P. Lussier
  • Patent number: 6924661
    Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.
    Type: Grant
    Filed: February 10, 2003
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, John M. Cohn, Kevin M. Grosselfinger, Susan K. Lichtensteiger, William F. Smith
  • Publication number: 20040155681
    Abstract: An integrated circuit structure has at least one voltage island and a pattern of power switches within the voltage island. The pattern determines the number of (and evenly spaces) the power switches according to the size of the serviceable area to which each of the power switches can provide power. The size of the power switches are matched to the current and voltage that will be provided by the power buses. The size of the serviceable area to which each of the power switches can provide power is dependent upon the size of the power switches.
    Type: Application
    Filed: February 10, 2003
    Publication date: August 12, 2004
    Applicant: International Business Machines Corporation
    Inventors: Patrick H. Buffet, John M. Cohn, Kevin M. Grosselfinger, Susan K. Lichtensteiger, William F. Smith
  • Patent number: 6762367
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: July 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Publication number: 20040132229
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Application
    Filed: December 17, 2003
    Publication date: July 8, 2004
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Publication number: 20040061519
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Application
    Filed: September 20, 2003
    Publication date: April 1, 2004
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Publication number: 20040050585
    Abstract: In the present invention an electronic package assembly includes an integrated circuit positioned on a substrate. The substrate has substantially horizontal layers including horizontal signal wires having vertical thicknesses and resistance. In a preferred embodiment, first and second vertical thicknesses of the signal wires alternate from the top to the bottom of the substrate such that the signal wires with greater vertical thicknesses have lower resistance than the signal wires would typically have. A plurality of substantially vertical conductive vias traverse the horizontal layers such that the vertical conductive vias connect to the integrated circuit and connect with at least one of the horizontal signal wires. A circuit board positioned beneath the substrate includes connection members for connecting with, and terminating the vertical conductive vias.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 18, 2004
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet
  • Patent number: 6703706
    Abstract: An electrical structure to optimize a signal wire structure. The electrical structure provides concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: March 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron
  • Patent number: 6677774
    Abstract: A method for improving the signal-to-noise ratio in an IDDQ defect test is disclosed. An integrated circuit is divided into a plurality of areas and each area is provided with and bounded by terminals. An IDDQ defect is activated to generate IDDQ defect current within the integrated circuit. An amount of IDDQ defect current generated within each area is measured at the terminals provided thereto. Based on the IDDQ current measurement on each area, an IDDQ current map is created. By analyzing the IDDQ current map, the presence and location of the defect is determined. Based on the determination, the IDDQ defect is isolated.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: January 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Douglas C. Heaberlin, Leah M. P. Pastel, Yu H. Sun
  • Patent number: 6631502
    Abstract: A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: October 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Joseph N. Kozhaya, Paul D. Montane, Robert A. Proctor, Erich C. Schanzenbach, Ivan L. Wemple
  • Patent number: 6606732
    Abstract: An automated method of selecting differential pairs in an integrated circuit comprising loading the design database for the integrated circuit package, and selecting output parameters for the differential pairs comprises adjacency criteria for the different pairs, time of flight tolerances for the differential pairs, and the redistribution layers and their voltage references. The method then includes comparing the output parameters to the design in the design database, and obtaining a resulting differential pairs list. The differential pair list preferably includes differential signal pairs having electrical characteristics within a predetermined design tolerance range. At least some of the differential signal pairs may comprise individual wires or connectors not physically adjacent one another.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 12, 2003
    Assignee: International Business Machines Corporation
    Inventors: Patrick H. Buffet, Craig Lussier, Joseph Natonio
  • Publication number: 20030135830
    Abstract: A method of analyzing the power distribution in a chip containing one or more voltage islands, each voltage island having a power distribution network connected to a chip-level power distribution network by one or more voltage translation interface circuits. The method comprising: analyzing the voltage-island power distribution networks independently of the chip-level power distribution network to obtain voltage translation interface circuit currents; using the voltage translation interface circuit currents as input to a model of the chip-level power distribution network to obtain voltage translation interface circuit input voltages; and calculating voltage translation interface circuit output voltages based on the voltage translation interface circuit input voltages, the voltage translation interface circuit currents, and current-voltage characteristics of the voltage translation interface circuits.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Inventors: Patrick H. Buffet, Joseph N. Kozhaya, Paul D. Montane, Robert A. Proctor, Erich C. Schanzenbach, Ivan L. Wemple
  • Publication number: 20030127728
    Abstract: The present invention relates to a method for optimization of a signal wire structure, providing concurrent optimization of a plurality of wire parameters, providing a plurality of wiring solutions, wherein each of said wiring solutions produces a wiring package having different wire parameters, providing an electronic package, determining the optimal wiring solutions for said electronic package; and producing an electronic package, using the optimized wiring package solutions. The resulting apparatus is also disclosed.
    Type: Application
    Filed: January 8, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Jean Audet, Timothy W. Budell, Patrick H. Buffet, Alain Caron