Patents by Inventor Patrick HANEKAMP

Patrick HANEKAMP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250057051
    Abstract: A layered structure includes a silicon-based substrate comprising a substrate surface; a titanium-copper seed layer arranged on the substrate surface, wherein the titanium-copper seed layer comprises a titanium layer and a copper layer, wherein the titanium layer is arranged on the substrate surface such that covalent bonds are formed between the titanium layer and silicon of the silicon-based substrate, and wherein the copper layer is arranged directly on the titanium layer, such that the titanium layer is arranged between the substrate surface and the copper layer; and a nickel-iron plating layer arranged directly on the copper layer of the titanium-copper seed layer such that the titanium-copper seed layer is arranged between the silicon-based substrate and the nickel-iron plating layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: Michael KIRSCH, Patrick HANEKAMP, Werner ROBL, Klemens PRÜGL, Juergen ZIMMER, Christoph OSWALD
  • Publication number: 20240357947
    Abstract: An electronic circuit includes a substrate and a superconducting electronic circuit unit which is constructed on the substrate. The superconducting electronic circuit unit includes a capacitor with parallel plates opposite one another and a crystalline capacitor dielectric arranged between the parallel plates.
    Type: Application
    Filed: April 15, 2024
    Publication date: October 24, 2024
    Inventors: Jochen BRAUMÜLLER, Florian BRANDL, Michael KIRSCH, Wolfgang RABERG, Nicolas ARLT, Jash BANKER, Patrick HANEKAMP
  • Publication number: 20230154978
    Abstract: A semiconductor device and a method of forming a semiconductor device are provided. In an embodiment, the semiconductor device comprises a device region, an edge termination region surrounding the device region, a first metal feature in the edge termination region, a first conformal ion diffusion barrier layer over the first metal feature, and a first conformal chemical protection layer over the first conformal ion diffusion barrier layer.
    Type: Application
    Filed: November 15, 2021
    Publication date: May 18, 2023
    Inventors: Carsten SCHAEFFER, Patrick HANEKAMP, Oliver HUMBEL, Angelika KOPROWSKI, Wolfgang LEHNERT, Francisco Javier SANTOS RODRIGUEZ